The duty cycle of the most significant bit from a 4-bit (0?9) BCD counter is ___

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Question
The duty cycle of the most significant bit from a 4-bit (0?9) BCD counter is ________.
Options
A. 10%
B. 20%
C. 50%
D. 80%

Correct Answer

20%

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2. A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.
Options
A. J and K inputs must both = 0
B. J must be 0, K doesn't matter
C. J doesn't matter, K must = 0
D. J must be 0 and K must be 1

4. Modulus refers to ________.
Options
A. a method used to fabricate decade counter units
B. the modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
C. an input on a counter that is used to set the counter state, such as UP/DOWN
D. the maximum number of states in a counter sequence

6. The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________.
Options
A. multiplexing, 1
B. parallel-to-serial conversion, 0
C. demultiplexing, 0
D. parallel-to-serial conversion, HIGH

7. In order to check the CLR function of a counter, ________.
Options
A. apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state
B. ground the CLR input and check to be sure that all of the Q outputs are LOW
C. connect the CLR input to V_cc and check to see if all of the Q outputs are HIGH
D. connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling

10. A(n) ________ one-shot starts a pulse in response to a trigger and will restart the internal pulse timer every time a subsequent trigger edge occurs before the pulse is complete.
Options
A. non-retriggerable
B. retriggerable
C. high-level triggered
D. edge-triggered

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