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- Question
The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.
Options- A. True
- B. False
- Correct Answer
- True
- 1. Which of the following testing procedures has one or more external moving parts?
Options- A. Bed-of-nails
- B. Flying probe
- C. EXTEST
- D. Boundary scan Discuss
- 2. A gated S-R flip-flop is in the hold condition whenever ________.
Options- A. the Gate Enable is HIGH
- B. the Gate Enable is LOW
- C. the S and R inputs are both LOW
- D. the Gate Enable is HIGH and the S and R inputs are both LOW Discuss
- 3. Offset is the characteristic of a DAC defined by the absence of any incorrect step reversals.
Options- A. True
- B. False Discuss
- 4. Zeros may be added to the left of the MSB to produce even groups of 4 bits when converting from binary to hexadecimal.
Options- A. True
- B. False Discuss
- 5. A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?
Options- A. 10002
- B. 10102
- C. 10112
- D. 11012 Discuss
- 6. The quantization error in an analog-to-digital converter can be reduced by:
Options- A. increasing the number of bits in the counter and DAC.
- B. decreasing the number of bits in the counter and increasing the number of bits in the DAC.
- C. increasing the number of bits in the counter and decreasing the number of bits in the DAC.
- D. decreasing the number of bits in the counter and DAC. Discuss
- 7. The process of reduction or simplification of combinational logic circuits increases the cost of the circuit.
Options- A. True
- B. False Discuss
- 8. A logic probe is placed on the output of a digital circuit and the probe lamp is dimly lit. This display indicates ________.
Options- A. that an open or bad logic level exists
- B. a high level output
- C. a high-frequency pulse train
- D. that the supply voltage is low Discuss
- 9. The AND, OR, and TEST instructions are all part of which type of instruction?
Options- A. Data transfer
- B. Arithmetic
- C. Bit manipulation
- D. Loops and jumps Discuss
- 10. Settling time is normally defined as the time it takes a DAC to settle within ________.
Options- A.
1/8 LSB of its final value when a change occurs in the input code - B. 1/4 LSB of its final value when a change occurs in the input code
- C. 1/2 LSB of its final value when a change occurs in the input code
- D. 1 LSB of its final value when a change occurs in the input code Discuss
More questions
Correct Answer: Flying probe
Correct Answer: the Gate Enable is HIGH and the S and R inputs are both LOW
Correct Answer: False
Correct Answer: True
Correct Answer: 10002
Correct Answer: increasing the number of bits in the counter and DAC.
Correct Answer: False
Correct Answer: that an open or bad logic level exists
Correct Answer: Bit manipulation
Correct Answer:
1/2 LSB of its final value when a change occurs in the input code Comments
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