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  • Question

  • Parallel in/parallel out registers have parallel input and output busses.


  • Options
  • A. True
  • B. False

  • Correct Answer
  • True 

    • Counters problems

    Search Results

    • 1. Bidirectional shift registers can shift data either right or left.

    • Options
    • A. True
    • B. False
      • Discuss
    • 2. An effective time delay device can be constructed by using the propagation delay characteristic of parallel shift registers.

    • Options
    • A. True
    • B. False
      • Discuss
    • 3. Once an up/down counter begins its count sequence, it cannot be reversed.

    • Options
    • A. True
    • B. False
      • Discuss
    • 4. Shift register counters use logic functions to reset the registers when the desired count is reached.

    • Options
    • A. True
    • B. False
      • Discuss
    • 5. To cascade is to connect in parallel.

    • Options
    • A. True
    • B. False
      • Discuss
    • 6. A glitch is a short pulse resulting in an undesired result in a digital circuit.

    • Options
    • A. True
    • B. False
      • Discuss
    • 7. The term synchronous refers to events that do not occur at the same time.

    • Options
    • A. True
    • B. False
      • Discuss
    • 8. The modulus of a counter is the actual number of states in its sequence.

    • Options
    • A. True
    • B. False
      • Discuss
    • 9. All decade counters are BCD counters.

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. In VHDL, when we want to remember a value it must be stored in a VARIABLE.

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    • A. True
    • B. False
      • Discuss

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