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  • Question

  • Assume an Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ___ latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.


  • Options
  • A. Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ___
  • B. Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ___
  • C. Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ___
  • D. Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ___

  • Correct Answer
  •  

    • Flip-Flops problems

    Search Results

    • 1. The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.

    • Options
    • A. logic level
    • B. flip-flop
    • C. edge-detector circuit
    • D. toggle detector
      • Discuss
    • 2. The ________ is the time interval immediately following the active transition of the clock signal.

    • Options
    • A. hold time
    • B. setup time
    • C. over-time
    • D. hang-time
      • Discuss
    • 3. The action of ________ a FF or latch is also called resetting.

    • Options
    • A. breaking
    • B. clearing
    • C. freeing
    • D. changing
      • Discuss
    • 4. A major drawback to an latch is its ________.

    • Options
    • A. complexity
    • B. slow speed
    • C. invalid condition
    • D. latch mode
      • Discuss
    • 5. The advantage of a J-K flip-flop over an S-R FF is that ________.

    • Options
    • A. it has fewer gates
    • B. it has only one output
    • C. it has no invalid states
    • D. it does not require a clock input
      • Discuss
    • 6. The term hold always means ________.

    • Options
    • A.
    • B.
    • C.
    • D. no change
      • Discuss
    • 7. The asynchronous inputs on a J-K flip-flop ________.

    • Options
    • A. are normally not at the active level at the same time
    • B. take precedence over the J and K inputs
    • C. do not require a clock pulse to affect the output
    • D. all of the above
      • Discuss
    • 8. A flip-flop operation is described as a toggle when the result after a clock is ________.

    • Options
    • A.
    • B.
    • C.
    • D. change to opposite states
      • Discuss
    • 9. The duty cycle of a 555 timer configured as a basic astable multivibrator is controlled by ________.

    • Options
    • A. one resistor
    • B. two resistors
    • C. one capacitor
    • D. a resistor and a capacitor
      • Discuss
    • 10. When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.

    • Options
    • A. be invalid
    • B. not change
    • C. remain unchanged
    • D. toggle
      • Discuss

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