Curioustab

Home » Digital Electronics » Flip-Flops

When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.

be invalid
not change
remain unchanged
toggle

Correct Answer: toggle

← Previous Question Next Question→

More Questions from Flip-Flops

The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.
An astable multivibrator is a circuit that ________.
If data is brought into the J terminal and its complement to the K terminal, a J-K flip-flop operates as a(n) ________.

Discussion & Comments

No comments yet. Be the first to comment!

Join Discussion