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  • Question

  • A major drawback to an A major drawback to an latch is its ________. complexity slow speed invalid condition latch modelatch is its ________.


  • Options
  • A. complexity
  • B. slow speed
  • C. invalid condition
  • D. latch mode

  • Correct Answer
  • invalid condition 

    • Flip-Flops problems

    Search Results

    • 1. The advantage of a J-K flip-flop over an S-R FF is that ________.

    • Options
    • A. it has fewer gates
    • B. it has only one output
    • C. it has no invalid states
    • D. it does not require a clock input
      • Discuss
    • 2. When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.

    • Options
    • A. S = 1, R = 1
    • B. S = 1, R = 0
    • C. S = 0, R = 1
    • D. S = 0, R = 0
      • Discuss
    • 3. The postponed symbol () on the output of a flip-flop identifies it as being ________.

    • Options
    • A. a D flip-flop
    • B. a J-K flip-flop
    • C. pulse triggered
    • D. trailing edge-triggered
      • Discuss
    • 4. A gated S-R flip-flop is in the hold condition whenever ________.

    • Options
    • A. the Gate Enable is HIGH
    • B. the Gate Enable is LOW
    • C. the S and R inputs are both LOW
    • D. the Gate Enable is HIGH and the S and R inputs are both LOW
      • Discuss
    • 5. A positive edge-triggered flip-flop will accept inputs only when the clock ________.

    • Options
    • A. is LOW
    • B. changes from HIGH to LOW
    • C. is HIGH
    • D. changes from LOW to HIGH
      • Discuss
    • 6. The action of ________ a FF or latch is also called resetting.

    • Options
    • A. breaking
    • B. clearing
    • C. freeing
    • D. changing
      • Discuss
    • 7. The ________ is the time interval immediately following the active transition of the clock signal.

    • Options
    • A. hold time
    • B. setup time
    • C. over-time
    • D. hang-time
      • Discuss
    • 8. The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.

    • Options
    • A. logic level
    • B. flip-flop
    • C. edge-detector circuit
    • D. toggle detector
      • Discuss
    • 9. Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.

    • Options
    • A.
    • B.
    • C.
    • D.
      • Discuss
    • 10. The term hold always means ________.

    • Options
    • A.
    • B.
    • C.
    • D. no change
      • Discuss

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