When the output of the NOR gate S-R flip-flop is in the HOLD state (no change),

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Question
When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.
Options
A. S = 1, R = 1
B. S = 1, R = 0
C. S = 0, R = 1
D. S = 0, R = 0

Correct Answer

S = 0, R = 0

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2. A gated S-R flip-flop is in the hold condition whenever ________.
Options
A. the Gate Enable is HIGH
B. the Gate Enable is LOW
C. the S and R inputs are both LOW
D. the Gate Enable is HIGH and the S and R inputs are both LOW

5. The signal used to identify edge-triggered flip-flops is ________.
Options
A. a bubble on the clock input
B. an inverted "L" on the output
C. the letter "E" on the enable input
D. a triangle on the clock input

6. The advantage of a J-K flip-flop over an S-R FF is that ________.
Options
A. it has fewer gates
B. it has only one output
C. it has no invalid states
D. it does not require a clock input

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