A gated S-R flip-flop is in the hold condition whenever ________. the Gate Enabl

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Question
A gated S-R flip-flop is in the hold condition whenever ________.
Options
A. the Gate Enable is HIGH
B. the Gate Enable is LOW
C. the S and R inputs are both LOW
D. the Gate Enable is HIGH and the S and R inputs are both LOW

Correct Answer

the Gate Enable is HIGH and the S and R inputs are both LOW

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3. The signal used to identify edge-triggered flip-flops is ________.
Options
A. a bubble on the clock input
B. an inverted "L" on the output
C. the letter "E" on the enable input
D. a triangle on the clock input

4. A gated S-R flip-flop goes into the CLEAR condition when ________.
Options
A. S is HIGH; R is LOW; EN is HIGH
B. S is LOW; R is HIGH; EN is HIGH
C. S is LOW; R is HIGH; EN is LOW
D. S is HIGH; R is LOW; EN is LOW

8. The advantage of a J-K flip-flop over an S-R FF is that ________.
Options
A. it has fewer gates
B. it has only one output
C. it has no invalid states
D. it does not require a clock input

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