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  • Question

  • When the output of the NOR gate S-R flip-flop is Q = 0 and When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are: S = 1, R = 1 S = 1, R =, the inputs are:


  • Options
  • A. S = 1, R = 1
  • B. S = 1, R = 0
  • C. S = 0, R = 1
  • D. S = 0, R = 0

  • Correct Answer
  • S = 0, R = 1 

    • Flip-Flops problems

    Search Results

    • 1. Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a ________.

    • Options
    • A. PROCESS
    • B. computer
    • C. simulator
    • D. primitive library
      • Discuss
    • 2. The major advantage of a Schmitt trigger input is that it ________.

    • Options
    • A. avoids erratic triggering
    • B. has more triggering methods
    • C. has a wider range of outputs
    • D. can be retriggered
      • Discuss
    • 3. Most people would prefer to use ________ over HDL.

    • Options
    • A. graphic descriptions
    • B. functions
    • C. VHDL
    • D. AHDL
      • Discuss
    • 4. If an input is activated by a signal transition, it is ________.

    • Options
    • A. hair-triggered
    • B. line-triggered
    • C. pulse-triggered
    • D. edge-triggered
      • Discuss
    • 5. Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________.

    • Options
    • A. set
    • B. reset
    • C. latch
    • D. toggle
      • Discuss
    • 6. The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs.

    • Options
    • A. PRE, CLR, LOW
    • B. ON, OFF, HIGH
    • C. START, STOP, LOW
    • D. SET, RESET, HIGH
      • Discuss
    • 7. What type of multivibrator is a latch?

    • Options
    • A. Astable
    • B. Monostable
    • C. Bistable
    • D. It depends on the type of latch.
      • Discuss
    • 8. A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

    • Options
    • A. 3
    • B. 7
    • C. 10
    • D. 13
      • Discuss
    • 9. The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.


    • Options
    • A. point 4
    • B. points 3 and 4
    • C. points 1 and 2
    • D. points 4 and 5
      • Discuss
    • 10. A gated S-R flip-flop goes into the CLEAR condition when ________.

    • Options
    • A. S is HIGH; R is LOW; EN is HIGH
    • B. S is LOW; R is HIGH; EN is HIGH
    • C. S is LOW; R is HIGH; EN is LOW
    • D. S is HIGH; R is LOW; EN is LOW
      • Discuss

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