Discussion
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- Question
An input which can only be accepted when an enable or trigger is present is called asynchronous.
Options- A. True
- B. False
- Correct Answer
- False
- 1. The 7476 and 74LS76 are both dual flip-flops.
Options- A. True
- B. False Discuss
- 2. An astable multivibrator is sometimes referred to as a clock.
Options- A. True
- B. False Discuss
- 3. It takes four flip-flops to act as a divide-by-4 frequency divider.
Options- A. True
- B. False Discuss
- 4. ICs can perform sequential operations, including counting and data shifting.
Options- A. True
- B. False Discuss
- 5. A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.
Options- A. True
- B. False Discuss
- 6. The key to edge-triggered sequential circuits in VHDL is the ________.
Options- A. ARCHITECTURE
- B. PROCESS
- C. FUNCTION
- D. VARIABLE Discuss
- 7. Setup time specifies ________.
Options- A. the minimum time for the control levels to be maintained on the inputs prior to the triggering edge of the clock in order for data to be reliably clocked into the FF
- B. the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF
- C. how long the operator has in order to get the flip-flop running before the maximum power level is exceeded
- D. how long it takes the output to change states after the clock has transitioned Discuss
- 8. The inputs on a 7474 D flip-flop are S, R, D, and CLK ________ is/are synchronous.
Options- A. Only S
- B. S and R
- C. Only D
- D. All of the above. Discuss
- 9. An edge-triggered flip-flop can change states only when ________.
Options- A. the trigger is HIGH
- B. the D input is HIGH
- C. the trigger is LOW
- D. the trigger input changes levels Discuss
- 10. The 74121 nonretriggerable multivibrator can have the output pulse set by a single external component. This component is a(n) ________.
Options- A. capacitor
- B. inductor
- C. resistor
- D. LED Discuss
Flip-Flops problems
Search Results
Correct Answer: True
Correct Answer: True
Correct Answer: False
Correct Answer: True
Correct Answer: False
Correct Answer: PROCESS
Correct Answer: the minimum time for the control levels to be maintained on the inputs prior to the triggering edge of the clock in order for data to be reliably clocked into the FF
Correct Answer: All of the above.
Correct Answer: the trigger input changes levels
Correct Answer: capacitor
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