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Home ‣ Digital Electronics ‣ Flip-Flops Comments
  • Question

  • Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.


  • Options
  • A. True
  • B. False

  • Correct Answer
  • True 

    • Flip-Flops problems

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    • 1. A one-shot circuit is also known as a timer.

    • Options
    • A. True
    • B. False
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    • 2. The S-R flip-flop has no invalid or unused state.

    • Options
    • A. True
    • B. False
      • Discuss
    • 3. The Q output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.

    • Options
    • A. True
    • B. False
      • Discuss
    • 4. The 555 timer can be used in either the astable or monostable modes.

    • Options
    • A. True
    • B. False
      • Discuss
    • 5. Simple gate circuits, combinational logic, and transparent S-R flip-flops are synchronous.

    • Options
    • A. True
    • B. False
      • Discuss
    • 6. Inputs that cause the output of a flip-flop to change instantaneously are asynchronous.

    • Options
    • A. True
    • B. False
      • Discuss
    • 7. When the output of the NOR gate S-R flip-flop is and , the inputs are .

    • Options
    • A. True
    • B. False
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    • 8. Some flip-flops have invalid states.

    • Options
    • A. True
    • B. False
      • Discuss
    • 9. A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. ICs can perform sequential operations, including counting and data shifting.

    • Options
    • A. True
    • B. False
      • Discuss

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