Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.
Options
A. True
B. False
Correct Answer
True
More questions
1. A sample-and-hold circuit is used in D/A conversion.
5. An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 µs. The output that has the proper delay is ________.