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Home ‣ Digital Electronics ‣ Flip-Flops Comments
  • Question

  • The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.


  • Options
  • A. True
  • B. False

  • Correct Answer
  • True 

    • Flip-Flops problems

    Search Results

    • 1. A flip-flop is in the CLEAR condition when .

    • Options
    • A. True
    • B. False
      • Discuss
    • 2. A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.

    • Options
    • A. True
    • B. False
      • Discuss
    • 3. The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as logic standard primitives.

    • Options
    • A. True
    • B. False
      • Discuss
    • 4. Parallel data transfers between two different sets of registers require more than one shift pulse.

    • Options
    • A. True
    • B. False
      • Discuss
    • 5. The term CLEAR always means that .

    • Options
    • A. True
    • B. False
      • Discuss
    • 6. A D latch has one data-input line.

    • Options
    • A. True
    • B. False
      • Discuss
    • 7. The 7474 has two distinct types of inputs: synchronous and asynchronous.

    • Options
    • A. True
    • B. False
      • Discuss
    • 8. The gated S-R flip-flop is asynchronous.

    • Options
    • A. True
    • B. False
      • Discuss
    • 9. Using knowledge from previous chapters, an S-R flip-flop circuit is easy to design.

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.

    • Options
    • A. True
    • B. False
      • Discuss

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