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Home ‣ Digital Electronics ‣ Flip-Flops Comments
  • Question

  • A negative edge-triggered flip-flop will accept inputs only when the clock is LOW.


  • Options
  • A. True
  • B. False

  • Correct Answer
  • False 

    • Flip-Flops problems

    Search Results

    • 1. A D-type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.

    • Options
    • A. True
    • B. False
      • Discuss
    • 2. A J-K flip-flop and associated waveforms are shown below. The circuit is operating properly.


    • Options
    • A. True
    • B. False
      • Discuss
    • 3. Edge-triggered flip-flops can be identified by the triangle on the clock input.

    • Options
    • A. True
    • B. False
      • Discuss
    • 4. PRESET and CLEAR inputs are normally synchronous.

    • Options
    • A. True
    • B. False
      • Discuss
    • 5. In VHDL, each instance of a component is given a name followed by a semicolon and the name of the library primitive.

    • Options
    • A. True
    • B. False
      • Discuss
    • 6. Latches are tristate devices whose state normally depends on asynchronous inputs.

    • Options
    • A. True
    • B. False
      • Discuss
    • 7. The term CLEAR always means that .

    • Options
    • A. True
    • B. False
      • Discuss
    • 8. Parallel data transfers between two different sets of registers require more than one shift pulse.

    • Options
    • A. True
    • B. False
      • Discuss
    • 9. The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as logic standard primitives.

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.

    • Options
    • A. True
    • B. False
      • Discuss

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