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  • Question
  • The equation ________ cannot be further simplified.


  • Options
  • A. The equation ________ cannot be further simplified.
  • B. The equation ________ cannot be further simplified.
  • C. The equation ________ cannot be further simplified.
  • D. The equation ________ cannot be further simplified.

  • Correct Answer
  •  


  • Combinational Logic Circuits problems


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    • 1. Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in ________ terms in the K-map and can be treated as either ________ or ________, in order to ________ the resulting term.

    • Options
    • A. don't care, 1's, 0's, simplify
    • B. spurious, AND's, OR's, eliminate
    • C. duplicate, 1's, 0's, verify
    • D. spurious, 1's, 0's, simplify
    • Discuss
    • 2. A half-adder does not have ________.

    • Options
    • A. carry in
    • B. carry out
    • C. two inputs
    • D. all of the above
    • Discuss
    • 3. When an open occurs on the input of a TTL device, the output will ________.

    • Options
    • A. go LOW, because there is no current in an open circuit
    • B. react as if the open input were a HIGH
    • C. go HIGH, since full voltage appears across an open
    • D. still be good, if only the good inputs are used
    • Discuss
    • 4. Parity generators and checkers use ________ gates.

    • Options
    • A. exclusive-AND
    • B. exclusive-OR/NOR
    • C. exclusive-OR
    • D. exclusive-NAND
    • Discuss
    • 5. In an odd-parity system, the data that will produce a parity bit = 1 is ________.

    • Options
    • A. data = 1010011
    • B. data = 1111000
    • C. data = 1100000
    • D. All of the above
    • Discuss
    • 6. The Boolean equation ________ results from this Karnaugh map.


    • Options
    • A.
    • B.
    • C.
    • D.
    • Discuss
    • 7. Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected ________.

    • Options
    • A. to the outputs from the least significant 4-bit comparator
    • B. to the cascading inputs of the least significant 4-bit comparator
    • C. A = B to a logic high, A < b and a > B to a logic low
    • D. ground
    • Discuss
    • 8. The AND-OR-INVERT gates are designed to simplify implementation of ________.

    • Options
    • A. POS logic
    • B. DeMorgan's theorem
    • C. NAND logic
    • D. SOP logic
    • Discuss
    • 9. The Boolean equation ________ results from this Karnaugh map.


    • Options
    • A.
    • B.
    • C.
    • D.
    • Discuss
    • 10. The final output of a POS circuit is generated by ________.

    • Options
    • A. an AND
    • B. an OR
    • C. a NOR
    • D. a NAND
    • Discuss


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