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  • Question
  • Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the QH output?


  • Options
  • A. 1
  • B. 7
  • C. 8
  • D. 9

  • Correct Answer



  • Shift Registers problems


    Search Results


    • 1. Shifting a binary number to the left by one position is equivalent to ________.

    • Options
    • A. multiplying by two
    • B. multiplying by four
    • C. dividing by two
    • D. dividing by four
    • Discuss
    • 2. Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?

    • Options
    • A. 0
    • B. 1
    • C. 2
    • D. 3
    • Discuss
    • 3. An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 µs. The output that has the proper delay is ________.

    • Options
    • A. QE
    • B. QF
    • C. QG
    • D. QH
    • Discuss
    • 4. A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________.

    • Options
    • A. parallel in/serial out
    • B. serial in/parallel out
    • C. serial in/serial out
    • D. parallel in/parallel out
    • Discuss
    • 5. Assume a 4-bit Johnson counter is initially cleared. After the first clock pulse the output is 0001. After the next clock pulse the output will be ________.

    • Options
    • A. 0011
    • B. 0010
    • C. 1000
    • D. 0110
    • Discuss
    • 6. A burst refresh and a normal memory operation of a DRAM can be interspersed.

    • Options
    • A. True
    • B. False
    • Discuss
    • 7. The address-decoding scheme for a 16K-byte EPROM memory system requires a 1-to-8-address decoder when 4K × 8 memory is used.

    • Options
    • A. True
    • B. False
    • Discuss
    • 8. Main computer memory is usually DRAM because of its high density and low cost; cache memory is usually SRAM because of its high speed.

    • Options
    • A. True
    • B. False
    • Discuss
    • 9. Testing and troubleshooting the decoding logic will not reveal problems with the memory chips and their connections to the CPU busses.

    • Options
    • A. True
    • B. False
    • Discuss
    • 10. Fusible-link PROMs are programmed by removing the desired fuse links using a microscope and tweezers.

    • Options
    • A. True
    • B. False
    • Discuss


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