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Home ‣ Digital Electronics ‣ Logic Gates See What Others Are Saying!
  • Question

  • The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.

    The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and


  • Options
  • A. a steady LOW
  • B. a steady HIGH
  • C. an undefined level
  • D. pulses

  • Correct Answer
  • a steady LOW 

    • More questions

    • 1. CPLDs and FPGAs are often referred to as high-capacity programmable logic devices (HCPLDs).

    • Options
    • A. True
    • B. False
      • Discuss
    • 2. Based on the indications of probe A in the figure given below, what is wrong, if anything, with the circuit?


    • Options
    • A. The logic probe is unable to determine the state of the circuit at that point and is blinking to alert the technician to the problem.
    • B. The output appears to be shorted to Vcc, but is being pulsed by the pulser.
    • C. The output appears to be LOW, but is being pulsed by the pulser.
    • D. Nothing appears to be wrong at that point.
      • Discuss
    • 3. The BCD number for decimal 16 is ________.

    • Options
    • A. 00010110
    • B. 00010000
    • C. 00010010
    • D. 11100000
      • Discuss
    • 4. Solve this binary problem: 01000110 ÷ 00001010 =

    • Options
    • A. 0111
    • B. 10011
    • C. 1001
    • D. 0011
      • Discuss
    • 5. Which digital system translates coded characters into a more useful form?

    • Options
    • A. encoder
    • B. display
    • C. counter
    • D. decoder
      • Discuss
    • 6. The expression can be directly implemented using only ________.

    • Options
    • A. an XOR gate
    • B. an XNOR gate
    • C. an AOI circuit
    • D. three 2-input NAND gates
      • Discuss
    • 7. D/A conversion is the process of taking a voltage or current and converting it to a digital code.

    • Options
    • A. True
    • B. False
      • Discuss
    • 8. ________ output levels would not be a valid LOW for a TTL gate.

    • Options
    • A. 0.2 V
    • B. 0.3 V
    • C. 0.5 V
    • D. All of the above.
      • Discuss
    • 9. DMA is particularly suited for data transfer between the ________.

    • Options
    • A. disk drive and CPU
    • B. disk drive and RAM
    • C. disk drive and ROM
    • D. disk drive and I/O
      • Discuss
    • 10. Which is not part of the execution unit (EU)?

    • Options
    • A. Arithmetic logic unit (ALU)
    • B. Clock
    • C. General registers
    • D. Flags
      • Discuss

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