The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.
Options
A. a steady LOW
B. a steady HIGH
C. an undefined level
D. pulses
Correct Answer
a steady LOW
More questions
1. The systems shown in the given figure communicate using ________.
9. In HDL when a circuit is simulated on a computer, the designer must create all the different scenarios that will be experienced by the actual circuit and must also know the proper response to those inputs.