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- Question
Which microprocessor has multiplexed data and address lines?
Options- A. 8086/8088
- B. 80286
- C. 80386
- D. Pentium
- Correct Answer
- 8086/8088
- 1. All flip-flops in an asynchronous counter change states at the same time.
Options- A. True
- B. False Discuss
- 2. A GAL is essentially a ________.
Options- A. non-reprogrammable PAL
- B. PAL that is programmed only by the manufacturer
- C. very large PAL
- D. reprogrammable PAL Discuss
- 3. Totem-pole outputs ________ be connected ________ because ________.
Options- A. can, in parallel, sometimes higher current is required
- B. cannot, together, if the outputs are in opposite states excessively high currents can damage one or both devices
- C. should, in series, certain applications may require higher output voltage
- D. can, together, together they can handle larger load currents and higher output voltages Discuss
- 4. In the automatic reset circuit for a flip-flop, how long does it take the capacitor to completely charge?
Options- A. 1 time constant (RC)
- B. 2 time constants (RC)
- C. 5 time constants (RC)
- D. 10 time constants (RC) Discuss
- 5. A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q output of each stage of the counter?
Options- A. Q1 = 22 MHz, Q2 = 11 MHz, Q3 = 5.5 MHz, Q4 = 2.75 MHz
- B. Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz
- C. Q1 = 11 MHz, Q2 = 11 MHz, Q3 = 11 MHz, Q4 = 11 MHz
- D. Q1 = 22 MHz, Q2 = 22 MHz, Q3 = 22 MHz, Q4 = 22 MHz Discuss
- 6. A write operation may also be referred to as a "fetch" operation.
Options- A. True
- B. False Discuss
- 7. A major drawback in using ECL logic circuits in conjunction with TTL and MOS circuits is its negative supply voltages and logic levels.
Options- A. True
- B. False Discuss
- 8. Edge-triggered flip-flops must have:
Options- A. very fast response times
- B. at least two inputs to handle rising and falling edges
- C. positive edge-detection circuits
- D. negative edge-detection circuits Discuss
- 9. A positive edge-triggered D flip-flop will store a 1 when ________.
Options- A. the D input is HIGH and the clock transitions from HIGH to LOW
- B. the D input is HIGH and the clock transitions from LOW to HIGH
- C. the D input is HIGH and the clock is LOW
- D. the D input is HIGH and the clock is HIGH Discuss
- 10. An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
Options- A.
- B.
- C.
- D.
Discuss
More questions
Correct Answer: False
Correct Answer: reprogrammable PAL
Correct Answer: cannot, together, if the outputs are in opposite states excessively high currents can damage one or both devices
Correct Answer: 5 time constants (RC)
Correct Answer: Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz
Correct Answer: False
Correct Answer: True
Correct Answer: positive edge-detection circuits
Correct Answer: the D input is HIGH and the clock transitions from LOW to HIGH
Correct Answer:
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