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Home Digital Electronics Digital System Projects Using HDL Comments

  • Question
  • In the digital clock project, what is the frequency of the MOD-6 counter in the minutes section?


  • Options
  • A. 1 pulse per minute
  • B. 6 pulses per minute
  • C. 10 pulses per minute
  • D. 1 pulse per hour

  • Correct Answer
  • 1 pulse per hour 


  • Digital System Projects Using HDL problems


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    • 1. In the frequency counter, when is the new count stored in the display register?

    • Options
    • A. After disabling the counter
    • B. When the count buffer is full
    • C. After the sample interval is set
    • D. When the timing and control block has put it there
    • Discuss
    • 2. Which is not a step used to define the scope of an HDL project?

    • Options
    • A. Are the inputs and outputs active HIGH or active LOW?
    • B. A clear vision of how to make each block work
    • C. What are the speed requirements?
    • D. How many bits of data are needed?
    • Discuss
    • 3. In a digital clock application, the basic frequency must be divided down to:

    • Options
    • A. 1 Hz.
    • B. 60 Hz.
    • C. 100 Hz.
    • D. 1000 Hz.
    • Discuss
    • 4. In the frequency counter, what is the function of the Schmitt trigger circuit?

    • Options
    • A. To reduce input noise
    • B. To condition the input signal
    • C. To convert non-square waveforms
    • D. To provide a usable signal to the display unit
    • Discuss
    • 5. In the digital clock project, the purpose of the frequency prescaler is to:

    • Options
    • A. find the basic frequency.
    • B. transform a 60 pps input to a 1 pps timing signal.
    • C. prevent the clock from exceeding 12:59:59.
    • D. allow the BCD display to have a value from 00?59.
    • Discuss
    • 6. In the frequency counter, if the clock generator produces a 100 kHz system clock signal, how many decade counters are required to measure 1 Hz?

    • Options
    • A. 6
    • B. 5
    • C. 4
    • D. 3
    • Discuss
    • 7. In the digital clock project, when does the PM indicator go high?

    • Options
    • A. Never
    • B. Going from 11:59:59 to 12:00:00
    • C. Going from 12:59:59 to 01:00:00
    • D. On the falling edge of the clock after enable goes high
    • Discuss
    • 8. Which is not a step in strategic planning for HDL development?

    • Options
    • A. There must be a way to test each piece.
    • B. Each block must fit together to make up the whole system.
    • C. The names of each input and output must be known.
    • D. The exact operation of each block must be thoroughly defined and understood.
    • Discuss
    • 9. In a frequency counter, what happens at high frequencies when the sampling interval is too long?

    • Options
    • A. The counter works fine.
    • B. The counter undercounts the frequency.
    • C. The measurement is less precise.
    • D. The counter overflows.
    • Discuss
    • 10. In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?

    • Options
    • A. It goes HIGH.
    • B. It goes LOW.
    • C. It goes to Hi-Z.
    • D. It goes to 1111H.
    • Discuss


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