Discussion
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- Question
Which is not a major block of an HDL frequency counter?
Options- A. Display register
- B. Decoder/display
- C. Timing and control unit
- D. Bit shifter
- Correct Answer
- Bit shifter
- 1. The accuracy of the frequency counter depends on the:
Options- A. system clock frequency.
- B. number of displayed digits.
- C. sampling rate.
- D. display update rate. Discuss
- 2. Why should a real hardware functional test be performed on the HDL stepper motor design?
Options- A. To check the speed of the software
- B. To check the current levels in the motor
- C. To check the voltage levels of the real outputs
- D. To provide a fully operational system Discuss
- 3. What does the major block of an HDL code emulation of a keypad include?
Options- A. A sequencer
- B. A clock
- C. A multiplexer
- D. A ring counter Discuss
- 4. How is the output frequency related to the sampling interval of a frequency counter?
Options- A. Directly with the sampling interval
- B. Inversely with the sampling interval
- C. More precision with longer sampling interval
- D. Less precision with longer sampling interval Discuss
- 5. In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?
Options- A. On
- B. Off
- C. Hi-Z
- D. 1011 Discuss
- 6. In the digital clock project, the purpose of the frequency prescaler is to:
Options- A. find the basic frequency.
- B. transform a 60 pps input to a 1 pps timing signal.
- C. prevent the clock from exceeding 12:59:59.
- D. allow the BCD display to have a value from 00?59. Discuss
- 7. In the frequency counter, what is the function of the Schmitt trigger circuit?
Options- A. To reduce input noise
- B. To condition the input signal
- C. To convert non-square waveforms
- D. To provide a usable signal to the display unit Discuss
- 8. In a digital clock application, the basic frequency must be divided down to:
Options- A. 1 Hz.
- B. 60 Hz.
- C. 100 Hz.
- D. 1000 Hz. Discuss
- 9. Which is not a step used to define the scope of an HDL project?
Options- A. Are the inputs and outputs active HIGH or active LOW?
- B. A clear vision of how to make each block work
- C. What are the speed requirements?
- D. How many bits of data are needed? Discuss
- 10. In the frequency counter, when is the new count stored in the display register?
Options- A. After disabling the counter
- B. When the count buffer is full
- C. After the sample interval is set
- D. When the timing and control block has put it there Discuss
Digital System Projects Using HDL problems
Search Results
Correct Answer: system clock frequency.
Correct Answer: To check the speed of the software
Correct Answer: A ring counter
Correct Answer: More precision with longer sampling interval
Correct Answer: Hi-Z
Correct Answer: transform a 60 pps input to a 1 pps timing signal.
Correct Answer: To convert non-square waveforms
Correct Answer: 1 Hz.
Correct Answer: A clear vision of how to make each block work
Correct Answer: After disabling the counter
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