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Home Digital Electronics Integrated-Circuit Logic Families Comments

  • Question
  • Which of the following logic families has the shortest propagation delay?


  • Options
  • A. S-TTL
  • B. AS-TTL
  • C. HS-TTL
  • D. HCMOS

  • Correct Answer
  • AS-TTL 


  • Integrated-Circuit Logic Families problems


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    • 1. What type of logic circuit is shown below and what logic function is being performed?


    • Options
    • A. It is an NMOS AND gate.
    • B. It is a CMOS AND gate.
    • C. It is a CMOS NOR gate.
    • D. It is a PMOS NAND gate.
    • Discuss
    • 2. Which of the logic families listed below allows the highest operating frequency?

    • Options
    • A. 74AS
    • B. ECL
    • C. HCMOS
    • D. 54S
    • Discuss
    • 3. What does ECL stand for?

    • Options
    • A. It stands for electron-coupled logic; all of the devices used within the gates are N-type transistors.
    • B. It stands for emitter-coupled logic; all of the inputs are coupled into the device through the emitters of the input transistors.
    • C. It stands for emitter-coupled logic; all of the emitters of the input transistors are connected together and each transistor functions as an emitter follower.
    • D. It stands for energy-coupled logic; the input energy is amplified by the input transistors and allows the device to deliver higher output currents.
    • Discuss
    • 4. The IEEE/ANSI notation of an internal underlined diamond denotes:

    • Options
    • A. totem-pole outputs.
    • B. open-collector outputs.
    • C. quadrature amplifiers.
    • D. tristate buffers.
    • Discuss
    • 5. Why is the fan-out of CMOS gates frequency dependent?

    • Options
    • A. Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate.
    • B. When the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal; this defines the upper operating frequency.
    • C. The higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.
    • D. The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of the driving gate.
    • Discuss
    • 6. Which of the following logic families has the highest noise margin?

    • Options
    • A. TTL
    • B. LS TTL
    • C. CMOS
    • D. HCMOS
    • Discuss
    • 7. What are the major differences between the 5400 and 7400 series of ICs?

    • Options
    • A. The 5400 series are military grade and require tighter supply voltages and temperatures.
    • B. The 5400 series are military grade and allow for a wider range of supply voltages and temperatures.
    • C. The 7400 series are an improvement over the original 5400s.
    • D. The 7400 series was originally developed by Texas Instruments. The 5400 series was brought out by National Semiconductors after TI's patents expired, as a second supply source.
    • Discuss
    • 8. Refer to the figure given below. What type of device is shown and what input levels are required to turn the LED off?


    • Options
    • A. The device is an open-collector AND gate and requires both inputs to be HIGH in order to turn the LED off.
    • B. The device is a Schottky AND gate and requires only one low input to turn the LED off.
    • C. The device is an open-collector AND gate and requires only one low input to turn the LED off.
    • D. The device is a Schottky open-collector AND gate and requires a low on both inputs to turn the LED off.
    • Discuss
    • 9. The bipolar TTL logic family that was developed to increase switching speed by preventing transistor saturation is:

    • Options
    • A. emitter-coupled logic (ECL).
    • B. current-mode logic (CML).
    • C. transistor-transistor logic (TTL).
    • D. emitter-coupled logic (ECL) and transistor-transistor logic (TTL).
    • Discuss
    • 10. Refer to the given figure. What type of output arrangement is being used for the output?


    • Options
    • A. Complementary-symmetry
    • B. Push-pull
    • C. Quasi push-pull
    • D. Totem-pole
    • Discuss


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