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Home Digital Electronics Programmable Logic Device Comments

  • Question
  • Now many times can a GAL be erased and reprogrammed?


  • Options
  • A. 0
  • B. At least 100
  • C. At least 1000
  • D. Over 10,000

  • Correct Answer
  • At least 100 


  • Programmable Logic Device problems


    Search Results


    • 1. How many macrocells are in a MAX700S LAB?

    • Options
    • A. 8
    • B. 16
    • C. 32
    • D. 64
    • Discuss
    • 2. Which is not a part of a GAL16V8's OLMC?

    • Options
    • A. TSMUX
    • B. OMUX
    • C. FMUX
    • D. PSMUX
    • Discuss
    • 3. FPGA is the acronym for ________.

    • Options
    • A. Flexible Programming [of] Generic Assemblies
    • B. Field Programmable Generic Array
    • C. Field Programmable Gate Array
    • D. Field Programmer's Gate Assembly
    • Discuss
    • 4. What is the input/output pin configuration of the GAL22V10?

    • Options
    • A. 10 output pins and 12 input pins
    • B. 2 special-purpose pins
    • C. 8 pins that are either inputs or outputs
    • D. All of the above
    • Discuss
    • 5. What is the major downfall of microprocessor/DSP systems?

    • Options
    • A. Speed?they are too fast
    • B. Speed?they are too slow
    • C. Too much flexibility
    • D. Not enough flexibility
    • Discuss
    • 6. The Altera MAX 7000 series ________.

    • Options
    • A. uses an E2PROM process technology
    • B. can have between 2 and 16 LABS and I/O control blocks
    • C. is available with DC supply voltages between 2.5 V and 5 V
    • D. all of the above
    • Discuss
    • 7. Which of the following testing procedures uses the JTAG IEEE standard?

    • Options
    • A. Bed-of-nails
    • B. Flying probe
    • C. EXTEST
    • D. Boundary scan
    • Discuss
    • 8. What is the defining difference between microprocessor/DSP systems and other digital systems?

    • Options
    • A. The digital system follows a programmed sequence of instructions that the designer specified.
    • B. The microprocessor follows a programmed sequence of instructions that the designer specified.
    • C. The digital system is faster.
    • D. The microprocessor/DSP is faster.
    • Discuss
    • 9. Each programmable array logic (PAL) gate product is applied to an OR gate and, if combinational logic is desired, the product is ORed and then:

    • Options
    • A. the polarity fuse is restored
    • B. sent to an inverter for output
    • C. sent immediately to an output pin
    • D. passed to the AND function for output
    • Discuss
    • 10. The complex programmable logic device (CPLD) contains several PAL-type simple programmable logic devices (SPLDs) called:

    • Options
    • A. macrocells
    • B. microcells
    • C. AND/OR arrays
    • D. fuse-link arrays
    • Discuss


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