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- Question
The output of this circuit is always ________.
Options- A. 1
- B. 0
- C. A
- D. A
- Correct Answer
- A
- 1. GAL is an acronym for ________.
Options- A. Generic Array Logic
- B. General Array Logic
- C. Giant Array Logic
- D. Generic Analysis Logic Discuss
- 2. The GAL16V8 has:
Options- A. 16 dedicated inputs.
- B. 8 special function pins.
- C. 8 pins that are used as inputs or outputs.
- D. All of the above Discuss
- 3. A slice consists of ________.
Options- A. only two logic cells
- B. between 2 and 8 logic cells
- C. up to 16 logic cells
- D. a single CLB Discuss
- 4. What is the status of a tristate output buffer on a MAX7000S family device?
Options- A. It is permanently enabled or disabled.
- B. It is controlled by one of the two global output enable pins.
- C. It is controlled by other inputs or functions generated by other macrocells.
- D. All of the above Discuss
- 5. What can the GAL22V10 do that the GAL16V8 cannot?
Options- A. It has an extra-large array.
- B. It is in-system programmable.
- C. It has twice the special function pins.
- D. All of the above Discuss
- 6. A macrocell basically contains ________.
Options- A. a programmable AND-OR gate array and some input buffers
- B. an OR-gate array and some output logic
- C. an AND-OR gate array and some output logic
- D. licensed programming Discuss
- 7. Product terms are the outputs of which type of gate within a PLD array?
Options- A. OR
- B. XOR
- C. AND
- D. flip-flop Discuss
- 8. A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations is a(n) ________.
Options- A. output logic macrocell
- B. look-up table
- C. parallel logic expander
- D. logic element Discuss
- 9. The output of this circuit is always ________.
Options- A. 1
- B. 0
- C. A
- D. A Discuss
- 10. Which of the following is true?
Options- A. Altera uses PAL architecture and Xilinx uses PLA architecture.
- B. Altera uses PLA architecture and Xilinx uses PAL architecture.
- C. Altera and Xilinx both use PAL architecture.
- D. Altera and Xilinx both use PLA architecture. Discuss
Programmable Logic Device problems
Search Results
Correct Answer: Generic Array Logic
Correct Answer: 8 pins that are used as inputs or outputs.
Correct Answer: only two logic cells
Correct Answer: All of the above
Correct Answer: It is in-system programmable.
Correct Answer: an OR-gate array and some output logic
Correct Answer: AND
Correct Answer: look-up table
Correct Answer: A
Correct Answer: Altera uses PAL architecture and Xilinx uses PLA architecture.
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