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  • Question

  • Referring to the given figure, what causes the Control FF to reset after D7?

    Referring to the given figure, what causes the Control FF to reset after D7? Once the data cycle is


  • Options
  • A. Once the data cycle is initiated by the Start bit, the one-shot produces an output pulse equal to the duration of the eight data bits. Once the eight data bits have been transferred to the data input register, the falling edge of the one-shot pulse resets the Control FF to start the sequence all over again.
  • B. After counting the eight data bits, the divide-by-8 counter produces an output on its active-LOW CLR line to reset the Control FF.
  • C. After counting eight clock pulses equivalent to eight data periods, the terminal count of the divide-by-8 counter and the clock trigger the one-shot, which in turn resets the Control FF and divide-by-8 circuits to begin the sequence all over again. Simultaneously the data is transferred through the output register.
  • D. When the data output register is full, it produces an output on its C terminal that triggers the one-shot, which in turn resets the Control FF.

  • Correct Answer
  • After counting eight clock pulses equivalent to eight data periods, the terminal count of the divide-by-8 counter and the clock trigger the one-shot, which in turn resets the Control FF and divide-by-8 circuits to begin the sequence all over again. Simultaneously the data is transferred through the output register. 

    • More questions

    • 1. The first microprocessor had a(n)________.

    • Options
    • A. 1-bit data bus
    • B. 2-bit data bus
    • C. 4-bit data bus
    • D. 8-bit data bus
      • Discuss
    • 2. If a 3-input OR gate has eight input possibilities, how many of those possibilities will result in a HIGH output?

    • Options
    • A. 1
    • B. 2
    • C. 7
    • D. 8
      • Discuss
    • 3. The select inputs to a multiplexer may also be called address lines.

    • Options
    • A. True
    • B. False
      • Discuss
    • 4. How many 2-input NOR gates does it take to produce a 2-input NAND gate?

    • Options
    • A. 1
    • B. 2
    • C. 3
    • D. 4
      • Discuss
    • 5. The 7476 and 74LS76 are both dual flip-flops.

    • Options
    • A. True
    • B. False
      • Discuss
    • 6. How many different states does a 3-bit asynchronous counter have?

    • Options
    • A. 2
    • B. 4
    • C. 8
    • D. 16
      • Discuss
    • 7. The invalid range for an input to TTL logic is from ________.

    • Options
    • A. 0 to 0.8 V
    • B. 1.2 to 1.6 V
    • C. 0.8 to 2.0 V
    • D. 2.0 to 5.0 V
      • Discuss
    • 8. A typical fan-out for most TTL is 9.

    • Options
    • A. True
    • B. False
      • Discuss
    • 9. The outputs of the 74138 octal decoder are enabled when the enable inputs are
      .

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. Convert the following hexadecimal number to decimal.
      B516

    • Options
    • A. 212
    • B. 197
    • C. 165
    • D. 181
      • Discuss

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