Which of the following is an example of a counter with a truncated modulus? 8 13

CuriousTab

CuriousTab

Home Aptitude

Discussion

Home ‣ Digital Electronics ‣ Counters Comments

Question
Which of the following is an example of a counter with a truncated modulus?
Options
A. 8
B. 13
C. 16
D. 32

Correct Answer

13

Counters problems

Search Results

4. Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
Options
A. input clock pulses are applied only to the first and last stages.
B. input clock pulses are applied only to the last stage.
C. input clock pulses are applied simultaneously to each stage.
D. input clock pulses are not used to activate any of the counter stages.

6. Which of the following procedures could be used to check the parallel loading feature of a counter?
Options
A. Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs.
B. Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.
C. Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.
D. Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs.

7. Referring to the given figure, what causes the Control FF to reset after D7?
Options
A. Once the data cycle is initiated by the Start bit, the one-shot produces an output pulse equal to the duration of the eight data bits. Once the eight data bits have been transferred to the data input register, the falling edge of the one-shot pulse resets the Control FF to start the sequence all over again.
B. After counting the eight data bits, the divide-by-8 counter produces an output on its active-LOW CLR line to reset the Control FF.
C. After counting eight clock pulses equivalent to eight data periods, the terminal count of the divide-by-8 counter and the clock trigger the one-shot, which in turn resets the Control FF and divide-by-8 circuits to begin the sequence all over again. Simultaneously the data is transferred through the output register.
D. When the data output register is full, it produces an output on its C terminal that triggers the one-shot, which in turn resets the Control FF.

8. The circuit given below has no output on Q₁when examined with an oscilloscope. All J-K inputs are HIGH, the CLK signal is present, and the Q₀ is toggling. The C input of FF₁ is a constant LOW. What could be causing the problem?
Options
A. The Q₀ output should be connected to the J input of FF₁.
B. The output of FF₀ may be shorted to ground.
C. The input of FF₁ may be shorted to ground.
D. Either the output of FF₀ or the input of FF₁ may be shorted to ground.

9. Which segments (by letter) of a seven-segment display need to be active in order to display a digit 6?
Options
A. b, c, d, e, f, and g
B. a, c, d, e, f, and g
C. a, b, c, d, and f
D. b, c, d, e, and f

10. For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________.
Options
A. C_p, the same clock input line
B. CE, the same clock input line
C. , the terminal count output
D. , both clock input lines

Comments

More in Digital Electronics: