What function will the counter shown below be performing during period "B" on th

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Question
What function will the counter shown below be performing during period "B" on the timing diagram?
Options
A. Counting up
B. Counting down
C. Inhibited
D. Loading

Correct Answer

Counting up

1. Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
Options
A. input clock pulses are applied only to the first and last stages.
B. input clock pulses are applied only to the last stage.
C. input clock pulses are applied simultaneously to each stage.
D. input clock pulses are not used to activate any of the counter stages.

9. Which of the following procedures could be used to check the parallel loading feature of a counter?
Options
A. Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs.
B. Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.
C. Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.
D. Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs.

10. Referring to the given figure, what causes the Control FF to reset after D7?
Options
A. Once the data cycle is initiated by the Start bit, the one-shot produces an output pulse equal to the duration of the eight data bits. Once the eight data bits have been transferred to the data input register, the falling edge of the one-shot pulse resets the Control FF to start the sequence all over again.
B. After counting the eight data bits, the divide-by-8 counter produces an output on its active-LOW CLR line to reset the Control FF.
C. After counting eight clock pulses equivalent to eight data periods, the terminal count of the divide-by-8 counter and the clock trigger the one-shot, which in turn resets the Control FF and divide-by-8 circuits to begin the sequence all over again. Simultaneously the data is transferred through the output register.
D. When the data output register is full, it produces an output on its C terminal that triggers the one-shot, which in turn resets the Control FF.

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