A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5

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Question
A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________.
Options
A. 10 kHz
B. 20 kHz
C. 30 kHz
D. 60 kHz

Correct Answer

30 kHz

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1. A multiplexed display being driven by a logic circuit:
Options
A. accepts data inputs from one line and passes this data to multiple output lines
B. accepts data inputs from several lines and allows one of them at a time to pass to the output
C. accepts data inputs from multiple lines and passes this data to multiple output lines
D. accepts data inputs from several lines and multiplexes this input data to four BCD lines

2. Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?
Options
A. Five flip-flops, three AND gates
B. Seven flip-flops, five AND gates
C. Four flip-flops, ten AND gates
D. Six flip-flops, four AND gates

3. Which segments of a seven-segment display would be required to be active to display the decimal digit 2?
Options
A. a, b, d, e, and g
B. a, b, c, d, and g
C. a, c, d, f, and g
D. a, b, c, d, e, and f

4. A MOD-16 synchronous counter has inputs labeled . These inputs would most probably be used to:
Options
A. reset the counter to 0000 at the end of each count cycle
B. preset the counter to a value determined by the inputs any time the is active-HIGH
C. preset the counter to a value determined by the inputs any time the is active-LOW
D. reset the counter to 0000 any time is active-HIGH and is active-LOW

9. Synchronous construction reduces the delay time of a counter to the delay of:
Options
A. all flip-flops and gates
B. all flip-flops and gates after a 3 count
C. a single gate
D. a single flip-flop and a gate

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