A 4-bit counter has a maximum modulus of ________. 3 6 8 16

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Question
A 4-bit counter has a maximum modulus of ________.
Options
A. 3
B. 6
C. 8
D. 16

Correct Answer

16

Counters problems

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1. How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?
Options
A. 128 gates, 6 inputs to each gate
B. 64 gates, 5 inputs to each gate
C. 64 gates, 6 inputs to each gate
D. 128 gates, 5 inputs to each gate

3. A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q output of each stage of the counter?
Options
A. Q₁ = 22 MHz, Q₂ = 11 MHz, Q₃ = 5.5 MHz, Q₄ = 2.75 MHz
B. Q₁ = 11 MHz, Q₂ = 5.5 MHz, Q₃ = 2.75 MHz, Q₄ = 1.375 MHz
C. Q₁ = 11 MHz, Q₂ = 11 MHz, Q₃ = 11 MHz, Q₄ = 11 MHz
D. Q₁ = 22 MHz, Q₂ = 22 MHz, Q₃ = 22 MHz, Q₄ = 22 MHz

4. Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.
Options
A. When MR₁ and MR₂ are both HIGH, all Qs will be reset to zero.
B. When MR₁ and MR₂ are both HIGH, all Qs will be reset to one.
C. MR₁ and MR₂ are provided to synchronously reset all four flip-flops.
D. To enable the count mode, MR₁ and MR₂ must be held LOW.

7. A seven-segment, common-anode LED display is designed for:
Options
A. all cathodes to be wired together
B. one common LED
C. a HIGH to turn off each segment
D. disorientation of segment modules

9. Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:
Options
A. input clock pulses are applied only to the first and last stages
B. input clock pulses are applied only to the last stage
C. input clock pulses are not used to activate any of the counter stages
D. input clock pulses are applied simultaneously to each stage

10. In an HDL ring counter, many invalid states are included in the programming by:
Options
A. using a case statement.
B. using an elsif statement.
C. including them under others.
D. the ser_in line.

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