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Counters
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Question
How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?
Options
A. 128 gates, 6 inputs to each gate
B. 64 gates, 5 inputs to each gate
C. 64 gates, 6 inputs to each gate
D. 128 gates, 5 inputs to each gate
Correct Answer
64 gates, 6 inputs to each gate
Counters problems
Search Results
1. The final output of a modulus-8 counter occurs one time for every ________.
Options
A. 8 clock pulses
B. 16 clock pulses
C. 24 clock pulses
D. 32 clock pulses
Show Answer
Scratch Pad
Discuss
Correct Answer: 8 clock pulses
2. A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the
Q
output of each stage of the counter?
Options
A.
Q
1
= 22 MHz,
Q
2
= 11 MHz,
Q
3
= 5.5 MHz,
Q
4
= 2.75 MHz
B.
Q
1
= 11 MHz,
Q
2
= 5.5 MHz,
Q
3
= 2.75 MHz,
Q
4
= 1.375 MHz
C.
Q
1
= 11 MHz,
Q
2
= 11 MHz,
Q
3
= 11 MHz,
Q
4
= 11 MHz
D.
Q
1
= 22 MHz,
Q
2
= 22 MHz,
Q
3
= 22 MHz,
Q
4
= 22 MHz
Show Answer
Scratch Pad
Discuss
Correct Answer:
Q
1
= 11 MHz,
Q
2
= 5.5 MHz,
Q
3
= 2.75 MHz,
Q
4
= 1.375 MHz
3. Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.
Options
A. When
MR
1
and
MR
2
are both HIGH, all
Q
s will be reset to zero.
B. When
MR
1
and
MR
2
are both HIGH, all
Q
s will be reset to one.
C.
MR
1
and
MR
2
are provided to synchronously reset all four flip-flops.
D. To enable the count mode,
MR
1
and
MR
2
must be held LOW.
Show Answer
Scratch Pad
Discuss
Correct Answer: When
MR
1
and
MR
2
are both HIGH, all
Q
s will be reset to zero.
4. What decimal value is required to produce an output at "X"?
Options
A. 1
B. 1 or 4
C. 2
D. 5
Show Answer
Scratch Pad
Discuss
Correct Answer: 5
5. Which of the following is a type of shift register counter?
Options
A. Decade
B. Binary
C. Ring
D. BCD
Show Answer
Scratch Pad
Discuss
Correct Answer: Ring
6. A 4-bit counter has a maximum modulus of ________.
Options
A. 3
B. 6
C. 8
D. 16
Show Answer
Scratch Pad
Discuss
Correct Answer: 16
7. How many data bits can be stored in the register shown below?
Options
A. 5
B. 32
C. 31
D. 4
Show Answer
Scratch Pad
Discuss
Correct Answer: 5
8. A seven-segment, common-anode LED display is designed for:
Options
A. all cathodes to be wired together
B. one common LED
C. a HIGH to turn off each segment
D. disorientation of segment modules
Show Answer
Scratch Pad
Discuss
Correct Answer: a HIGH to turn off each segment
9. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?
Options
A. None
B. One
C. Two
D. Fifteen
Show Answer
Scratch Pad
Discuss
Correct Answer: Fifteen
10. Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:
Options
A. input clock pulses are applied only to the first and last stages
B. input clock pulses are applied only to the last stage
C. input clock pulses are not used to activate any of the counter stages
D. input clock pulses are applied simultaneously to each stage
Show Answer
Scratch Pad
Discuss
Correct Answer: input clock pulses are applied simultaneously to each stage
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