Select the response that best describes the use of the Master Reset on typical 4

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Question
Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.
Options
A. When MR₁ and MR₂ are both HIGH, all Qs will be reset to zero.
B. When MR₁ and MR₂ are both HIGH, all Qs will be reset to one.
C. MR₁ and MR₂ are provided to synchronously reset all four flip-flops.
D. To enable the count mode, MR₁ and MR₂ must be held LOW.

Correct Answer

When MR₁ and MR₂ are both HIGH, all Qs will be reset to zero.

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3. What type of register is shown below?
Options
A. Parallel in/parallel out register
B. Serial in/parallel out register
C. Serial/parallel-in parallel-out register
D. Parallel-access shift register

4. To operate correctly, starting a ring counter requires:
Options
A. clearing one flip-flop and presetting all the others.
B. clearing all the flip-flops.
C. presetting one flip-flop and clearing all the others.
D. presetting all the flip-flops.

5. In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?
Options
A. A trigger edge has occurred and we must load the counter.
B. The counter is zero and we need to keep it at zero.
C. The shift register is reset.
D. The counter is not zero and we need to count down by one.

6. A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q output of each stage of the counter?
Options
A. Q₁ = 22 MHz, Q₂ = 11 MHz, Q₃ = 5.5 MHz, Q₄ = 2.75 MHz
B. Q₁ = 11 MHz, Q₂ = 5.5 MHz, Q₃ = 2.75 MHz, Q₄ = 1.375 MHz
C. Q₁ = 11 MHz, Q₂ = 11 MHz, Q₃ = 11 MHz, Q₄ = 11 MHz
D. Q₁ = 22 MHz, Q₂ = 22 MHz, Q₃ = 22 MHz, Q₄ = 22 MHz

8. How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?
Options
A. 128 gates, 6 inputs to each gate
B. 64 gates, 5 inputs to each gate
C. 64 gates, 6 inputs to each gate
D. 128 gates, 5 inputs to each gate

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