Discussion
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- Question
What decimal value is required to produce an output at "X"?
Options- A. 1
- B. 1 or 4
- C. 2
- D. 5
- Correct Answer
- 5
- 1. Which of the following is a type of shift register counter?
Options- A. Decade
- B. Binary
- C. Ring
- D. BCD Discuss
- 2. What type of register is shown below?
Options- A. Parallel in/parallel out register
- B. Serial in/parallel out register
- C. Serial/parallel-in parallel-out register
- D. Parallel-access shift register Discuss
- 3. To operate correctly, starting a ring counter requires:
Options- A. clearing one flip-flop and presetting all the others.
- B. clearing all the flip-flops.
- C. presetting one flip-flop and clearing all the others.
- D. presetting all the flip-flops. Discuss
- 4. In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?
Options- A. A trigger edge has occurred and we must load the counter.
- B. The counter is zero and we need to keep it at zero.
- C. The shift register is reset.
- D. The counter is not zero and we need to count down by one. Discuss
- 5. The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:
Options- A. external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
- B. modifying BCD counters to change states on every second input clock pulse
- C. modifying asynchronous counters to change states on every second input clock pulse
- D. elimination of the counter stages and the addition of combinational logic circuits to produce the desired counts Discuss
- 6. Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.
Options- A. When MR1 and MR2 are both HIGH, all Qs will be reset to zero.
- B. When MR1 and MR2 are both HIGH, all Qs will be reset to one.
- C. MR1 and MR2 are provided to synchronously reset all four flip-flops.
- D. To enable the count mode, MR1 and MR2 must be held LOW. Discuss
- 7. A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q output of each stage of the counter?
Options- A. Q1 = 22 MHz, Q2 = 11 MHz, Q3 = 5.5 MHz, Q4 = 2.75 MHz
- B. Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz
- C. Q1 = 11 MHz, Q2 = 11 MHz, Q3 = 11 MHz, Q4 = 11 MHz
- D. Q1 = 22 MHz, Q2 = 22 MHz, Q3 = 22 MHz, Q4 = 22 MHz Discuss
- 8. The final output of a modulus-8 counter occurs one time for every ________.
Options- A. 8 clock pulses
- B. 16 clock pulses
- C. 24 clock pulses
- D. 32 clock pulses Discuss
- 9. How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?
Options- A. 128 gates, 6 inputs to each gate
- B. 64 gates, 5 inputs to each gate
- C. 64 gates, 6 inputs to each gate
- D. 128 gates, 5 inputs to each gate Discuss
- 10. A 4-bit counter has a maximum modulus of ________.
Options- A. 3
- B. 6
- C. 8
- D. 16 Discuss
Counters problems
Search Results
Correct Answer: Ring
Correct Answer: Parallel-access shift register
Correct Answer: presetting one flip-flop and clearing all the others.
Correct Answer: The shift register is reset.
Correct Answer: external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
Correct Answer: When MR1 and MR2 are both HIGH, all Qs will be reset to zero.
Correct Answer: Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz
Correct Answer: 8 clock pulses
Correct Answer: 64 gates, 6 inputs to each gate
Correct Answer: 16
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