In a VHDL retriggerable edge-triggered one-shot, which condition will not exist

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Question
In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?
Options
A. A trigger edge has occurred and we must load the counter.
B. The counter is zero and we need to keep it at zero.
C. The shift register is reset.
D. The counter is not zero and we need to count down by one.

Correct Answer

The shift register is reset.

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1. The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:
Options
A. external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
B. modifying BCD counters to change states on every second input clock pulse
C. modifying asynchronous counters to change states on every second input clock pulse
D. elimination of the counter stages and the addition of combinational logic circuits to produce the desired counts

2. The circuit given below fails to produce data output. The individual flip-flops are checked with a logic probe and pulser, and each checks OK. What could be causing the problem?
Options
A. The data output line may be grounded.
B. One of the clock input lines may be open.
C. One of the interconnect lines between two stages may have a solder bridge to ground.
D. One of the flip-flops may have a solder bridge between its input and V_cc.

5. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.
Options
A. 15 ns
B. 30 ns
C. 45 ns
D. 60 ns

6. To operate correctly, starting a ring counter requires:
Options
A. clearing one flip-flop and presetting all the others.
B. clearing all the flip-flops.
C. presetting one flip-flop and clearing all the others.
D. presetting all the flip-flops.

7. What type of register is shown below?
Options
A. Parallel in/parallel out register
B. Serial in/parallel out register
C. Serial/parallel-in parallel-out register
D. Parallel-access shift register

10. Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.
Options
A. When MR₁ and MR₂ are both HIGH, all Qs will be reset to zero.
B. When MR₁ and MR₂ are both HIGH, all Qs will be reset to one.
C. MR₁ and MR₂ are provided to synchronously reset all four flip-flops.
D. To enable the count mode, MR₁ and MR₂ must be held LOW.

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