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- Question
A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.
Options- A. 15 ns
- B. 30 ns
- C. 45 ns
- D. 60 ns
- Correct Answer
- 60 ns
- 1. When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.
Options- A. product
- B. sum
- C. log
- D. reciprocal Discuss
- 2. One of the major drawbacks to the use of asynchronous counters is:
Options- A. low-frequency applications are limited because of internal propagation delays
- B. high-frequency applications are limited because of internal propagation delays
- C. asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications
- D. asynchronous counters do not have propagation delays and this limits their use in high-frequency applications Discuss
- 3. For a one-shot application, how can HDL code be used to make a circuit respond once to each positive transition on its trigger input?
Options- A. By using a counter
- B. By using an active clock
- C. By using an immediate reload
- D. By using edge trapping Discuss
- 4. The terminal count of a 3-bit binary counter in the DOWN mode is ________.
Options- A. 000
- B. 111
- C. 101
- D. 010 Discuss
- 5. Three cascaded decade counters will divide the input frequency by ________.
Options- A. 10
- B. 20
- C. 100
- D. 1,000 Discuss
- 6. List which pins need to be connected together on a 7492 to make a MOD-12 counter.
Options- A. 1 to 12, 11 to 6, 9 to 7
- B. 1 to 12, 12 to 6, 11 to 7
- C. 1 to 12, 9 to 6, 8 to 7
- D. 1 to 12 Discuss
- 7. How many flip-flops are required to construct a decade counter?
Options- A. 10
- B. 8
- C. 5
- D. 4 Discuss
- 8. The circuit given below fails to produce data output. The individual flip-flops are checked with a logic probe and pulser, and each checks OK. What could be causing the problem?
Options- A. The data output line may be grounded.
- B. One of the clock input lines may be open.
- C. One of the interconnect lines between two stages may have a solder bridge to ground.
- D. One of the flip-flops may have a solder bridge between its input and Vcc. Discuss
- 9. The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:
Options- A. external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
- B. modifying BCD counters to change states on every second input clock pulse
- C. modifying asynchronous counters to change states on every second input clock pulse
- D. elimination of the counter stages and the addition of combinational logic circuits to produce the desired counts Discuss
- 10. In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?
Options- A. A trigger edge has occurred and we must load the counter.
- B. The counter is zero and we need to keep it at zero.
- C. The shift register is reset.
- D. The counter is not zero and we need to count down by one. Discuss
Counters problems
Search Results
Correct Answer: product
Correct Answer: high-frequency applications are limited because of internal propagation delays
Correct Answer: By using edge trapping
Correct Answer: 000
Correct Answer: 1,000
Correct Answer: 1 to 12
Correct Answer: 4
Correct Answer: One of the clock input lines may be open.
Correct Answer: external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
Correct Answer: The shift register is reset.
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