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- Question
In VHDL, how many inputs will a primitive JK flip-flop have?
Options- A. 2
- B. 3
- C. 4
- D. 5
- Correct Answer
- 5
- 1. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:
Options- A. edge-detection circuit.
- B. NOR latch.
- C. NAND latch.
- D. pulse-steering circuit. Discuss
- 2. Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.
Options- A. True
- B. False Discuss
- 3. In VHDL, in which declaration section is a COMPONENT declared?
Options- A. Architecture
- B. Library
- C. Entity
- D. Port map Discuss
- 4. When is a flip-flop said to be transparent?
Options- A. when the Q output is opposite the input
- B. when the Q output follows the input
- C. when you can see through the IC packaging Discuss
- 5. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
Options- A. constantly LOW
- B. constantly HIGH
- C. a 20 kHz square wave
- D. a 10 kHz square wave Discuss
- 6. One example of the use of an S-R flip-flop is as a(n):
Options- A. racer
- B. astable oscillator
- C. binary storage register
- D. transition pulse generator Discuss
- 7. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
Options- A. 10.24 kHz
- B. 5 kHz
- C. 30.24 kHz
- D. 15 kHz Discuss
- 8. If an input is activated by a signal transition, it is ________.
Options- A. edge-triggered
- B. toggle triggered
- C. clock triggered
- D. noise triggered Discuss
- 9. Which of the following is correct for a gated D flip-flop?
Options- A. The output toggles if one of the inputs is held HIGH.
- B. Only one of the inputs can be HIGH at a time.
- C. The output complement follows the input when enabled.
- D. Q output follows the input D when the enable is HIGH. Discuss
- 10. What is one disadvantage of an S-R flip-flop?
Options- A. It has no enable input.
- B. It has an invalid state.
- C. It has no clock input.
- D. It has only a single output. Discuss
Flip-Flops problems
Search Results
Correct Answer: edge-detection circuit.
Correct Answer: False
Correct Answer: Architecture
Correct Answer: when the Q output follows the input
Correct Answer: a 10 kHz square wave
Correct Answer: binary storage register
Correct Answer: 5 kHz
Correct Answer: edge-triggered
Correct Answer: Q output follows the input D when the enable is HIGH.
Correct Answer: It has an invalid state.
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