Discussion
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- Question
The pulse width of a one-shot circuit is determined by ________.
Options- A. a resistor and capacitor
- B. two resistors
- C. two capacitors
- D. none of the above
- Correct Answer
- a resistor and capacitor
- 1. An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
Options- A.
- B.
- C.
- D.
Discuss
- 2. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
Options- A. CLK = NGT, D = 0
- B. CLK = PGT, D = 0
- C. CLOCK NGT, D = 1
- D. CLOCK PGT, D = 1
- E. CLK = NGT, D = 0, CLOCK NGT, D = 1 Discuss
- 3. Edge-triggered flip-flops must have:
Options- A. very fast response times
- B. at least two inputs to handle rising and falling edges
- C. positive edge-detection circuits
- D. negative edge-detection circuits Discuss
- 4. Which of the following is not generally associated with flip-flops?
Options- A. Hold time
- B. Propagation delay time
- C. Interval time
- D. Set up time Discuss
- 5. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
Options- A. No change will occur in the output.
- B. An invalid state will exist.
- C. The output will toggle.
- D. The output will reset. Discuss
- 6. Which of the following is correct for a D latch?
Options- A. The output toggles if one of the inputs is held HIGH.
- B. Q output follows the input D when the enable is HIGH.
- C. Only one of the inputs can be HIGH at a time.
- D. The output complement follows the input when enabled. Discuss
- 7. Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.
Options- A. True
- B. False Discuss
- 8. On a J-K flip-flop, when is the flip-flop in a hold condition?
Options- A. J = 0, K = 0
- B. J = 1, K = 0
- C. J = 0, K = 1
- D. J = 1, K = 1 Discuss
- 9. A positive edge-triggered D flip-flop will store a 1 when ________.
Options- A. the D input is HIGH and the clock transitions from HIGH to LOW
- B. the D input is HIGH and the clock transitions from LOW to HIGH
- C. the D input is HIGH and the clock is LOW
- D. the D input is HIGH and the clock is HIGH Discuss
- 10. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
Options- A. constantly LOW
- B. constantly HIGH
- C. a 20 kHz square wave
- D. a 10 kHz square wave Discuss
Flip-Flops problems
Search Results
Correct Answer:
Correct Answer: CLOCK PGT, D = 1
Correct Answer: positive edge-detection circuits
Correct Answer: Interval time
Correct Answer: No change will occur in the output.
Correct Answer: Q output follows the input D when the enable is HIGH.
Correct Answer: False
Correct Answer: J = 0, K = 0
Correct Answer: the D input is HIGH and the clock transitions from LOW to HIGH
Correct Answer: a 10 kHz square wave
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