Discussion
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- Question
A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
Options- A. CLK = NGT, D = 0
- B. CLK = PGT, D = 0
- C. CLOCK NGT, D = 1
- D. CLOCK PGT, D = 1
- E. CLK = NGT, D = 0, CLOCK NGT, D = 1
- Correct Answer
- CLOCK PGT, D = 1
- 1. Edge-triggered flip-flops must have:
Options- A. very fast response times
- B. at least two inputs to handle rising and falling edges
- C. positive edge-detection circuits
- D. negative edge-detection circuits Discuss
- 2. Which of the following is not generally associated with flip-flops?
Options- A. Hold time
- B. Propagation delay time
- C. Interval time
- D. Set up time Discuss
- 3. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
Options- A. No change will occur in the output.
- B. An invalid state will exist.
- C. The output will toggle.
- D. The output will reset. Discuss
- 4. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.
Options- A. 00
- B. 11
- C. 01
- D. 10 Discuss
- 5. A 555 operating as a monostable multivibrator has an R1 of 1 MΩ. Determine C1 for a pulse width of 2 s.
Options- A. 1.8 µF
- B. 18 F
- C. 18 pF
- D. 18 nF Discuss
- 6. An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
Options- A.
- B.
- C.
- D.
Discuss
- 7. The pulse width of a one-shot circuit is determined by ________.
Options- A. a resistor and capacitor
- B. two resistors
- C. two capacitors
- D. none of the above Discuss
- 8. Which of the following is correct for a D latch?
Options- A. The output toggles if one of the inputs is held HIGH.
- B. Q output follows the input D when the enable is HIGH.
- C. Only one of the inputs can be HIGH at a time.
- D. The output complement follows the input when enabled. Discuss
- 9. Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.
Options- A. True
- B. False Discuss
- 10. On a J-K flip-flop, when is the flip-flop in a hold condition?
Options- A. J = 0, K = 0
- B. J = 1, K = 0
- C. J = 0, K = 1
- D. J = 1, K = 1 Discuss
Flip-Flops problems
Search Results
Correct Answer: positive edge-detection circuits
Correct Answer: Interval time
Correct Answer: No change will occur in the output.
Correct Answer: 00
Correct Answer: 1.8 µF
Correct Answer:
Correct Answer: a resistor and capacitor
Correct Answer: Q output follows the input D when the enable is HIGH.
Correct Answer: False
Correct Answer: J = 0, K = 0
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