Edge-triggered flip-flops must have: very fast response times at least two input

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Question
Edge-triggered flip-flops must have:
Options
A. very fast response times
B. at least two inputs to handle rising and falling edges
C. positive edge-detection circuits
D. negative edge-detection circuits

Correct Answer

positive edge-detection circuits

Flip-Flops problems

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2. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
Options
A. No change will occur in the output.
B. An invalid state will exist.
C. The output will toggle.
D. The output will reset.

5. A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?
Options
A. The output is always low; the circuit is defective.
B. The Q output should be the complement of the output; the S and R terminals are reversed.
C. The Q should be following the R input; the R input is defective.
D. There is nothing wrong with the circuit.

6. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
Options
A. CLK = NGT, D = 0
B. CLK = PGT, D = 0
C. CLOCK NGT, D = 1
D. CLOCK PGT, D = 1
E. CLK = NGT, D = 0, CLOCK NGT, D = 1

9. Which of the following is correct for a D latch?
Options
A. The output toggles if one of the inputs is held HIGH.
B. Q output follows the input D when the enable is HIGH.
C. Only one of the inputs can be HIGH at a time.
D. The output complement follows the input when enabled.

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