Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as co

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Question
Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.
Options
A. 00
B. 11
C. 01
D. 10

Correct Answer

00

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2. A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?
Options
A. The output is always low; the circuit is defective.
B. The Q output should be the complement of the output; the S and R terminals are reversed.
C. The Q should be following the R input; the R input is defective.
D. There is nothing wrong with the circuit.

3. Which is not a real advantage of HDL?
Options
A. Using higher levels of abstraction
B. Tailoring components to exactly fit the needs of the project
C. The use of graphical tools
D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project

6. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
Options
A. No change will occur in the output.
B. An invalid state will exist.
C. The output will toggle.
D. The output will reset.

8. Edge-triggered flip-flops must have:
Options
A. very fast response times
B. at least two inputs to handle rising and falling edges
C. positive edge-detection circuits
D. negative edge-detection circuits

9. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
Options
A. CLK = NGT, D = 0
B. CLK = PGT, D = 0
C. CLOCK NGT, D = 1
D. CLOCK PGT, D = 1
E. CLK = NGT, D = 0, CLOCK NGT, D = 1

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