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- Question
A 555 operating as a monostable multivibrator has an R1 of 1 MΩ. Determine C1 for a pulse width of 2 s.
Options- A. 1.8 µF
- B. 18 F
- C. 18 pF
- D. 18 nF
- Correct Answer
- 1.8 µF
- 1. A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?
Options- A. The
output is always low; the circuit is defective. - B. The Q output should be the complement of the
output; the S and R terminals are reversed. - C. The Q should be following the R input; the R input is defective.
- D. There is nothing wrong with the circuit. Discuss
- 2. Which is not a real advantage of HDL?
Options- A. Using higher levels of abstraction
- B. Tailoring components to exactly fit the needs of the project
- C. The use of graphical tools
- D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project Discuss
- 3. A 555 operating as a monostable multivibrator has an R1 of 220 kΩ. Determine C1 for a pulse width of 4 ms.
Options- A. 0.017 µF
- B. 17 pF
- C. 170 pF
- D. 1,700 µF Discuss
- 4. For an S-R flip-flop to be set or reset, the respective input must be:
Options- A. installed with steering diodes
- B. in parallel with a limiting resistor
- C. LOW
- D. HIGH Discuss
- 5. A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?
Options- A. The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.
- B. The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.
- C. A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.
- D. A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop. Discuss
- 6. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.
Options- A. 00
- B. 11
- C. 01
- D. 10 Discuss
- 7. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
Options- A. No change will occur in the output.
- B. An invalid state will exist.
- C. The output will toggle.
- D. The output will reset. Discuss
- 8. Which of the following is not generally associated with flip-flops?
Options- A. Hold time
- B. Propagation delay time
- C. Interval time
- D. Set up time Discuss
- 9. Edge-triggered flip-flops must have:
Options- A. very fast response times
- B. at least two inputs to handle rising and falling edges
- C. positive edge-detection circuits
- D. negative edge-detection circuits Discuss
- 10. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
Options- A. CLK = NGT, D = 0
- B. CLK = PGT, D = 0
- C. CLOCK NGT, D = 1
- D. CLOCK PGT, D = 1
- E. CLK = NGT, D = 0, CLOCK NGT, D = 1 Discuss
Flip-Flops problems
Search Results
Correct Answer: The
output is always low; the circuit is defective. Correct Answer: The use of graphical tools
Correct Answer: 0.017 µF
Correct Answer: HIGH
Correct Answer: A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.
Correct Answer: 00
Correct Answer: No change will occur in the output.
Correct Answer: Interval time
Correct Answer: positive edge-detection circuits
Correct Answer: CLOCK PGT, D = 1
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