For an S-R flip-flop to be set or reset, the respective input must be: installed

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Question
For an S-R flip-flop to be set or reset, the respective input must be:
Options
A. installed with steering diodes
B. in parallel with a limiting resistor
C. LOW
D. HIGH

Correct Answer

HIGH

Flip-Flops problems

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1. A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?
Options
A. The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.
B. The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.
C. A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.
D. A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.

3. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
Options
A. The logic level at the D input is transferred to Q on NGT of CLK.
B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
C. The Q output is ALWAYS identical to the D input when CLK = PGT.
D. The Q output is ALWAYS identical to the D input.

5. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?
Options
A. An invalid state will exist.
B. No change will occur in the output.
C. The output will toggle.
D. The output will reset.

7. Which is not a real advantage of HDL?
Options
A. Using higher levels of abstraction
B. Tailoring components to exactly fit the needs of the project
C. The use of graphical tools
D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project

8. A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?
Options
A. The output is always low; the circuit is defective.
B. The Q output should be the complement of the output; the S and R terminals are reversed.
C. The Q should be following the R input; the R input is defective.
D. There is nothing wrong with the circuit.

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