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  • Question
  • How is a J-K flip-flop made to toggle?


  • Options
  • A. J = 0, K = 0
  • B. J = 1, K = 0
  • C. J = 0, K = 1
  • D. J = 1, K = 1

  • Correct Answer
  • J = 1, K = 1 


  • Flip-Flops problems


    Search Results


    • 1. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?

    • Options
    • A. An invalid state will exist.
    • B. No change will occur in the output.
    • C. The output will toggle.
    • D. The output will reset.
    • Discuss
    • 2. What is the significance of the J and K terminals on the J-K flip-flop?

    • Options
    • A. There is no known significance in their designations.
    • B. The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH.
    • C. The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
    • D. All of the other letters of the alphabet are already in use.
    • Discuss
    • 3. What is the difference between the enable input of the 7475 and the clock input of the 7474?

    • Options
    • A. The 7475 is edge-triggered.
    • B. The 7474 is edge-triggered.
    • Discuss
    • 4. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.

    • Options
    • A. SET
    • B. RESET
    • C. clear
    • D. invalid
    • Discuss
    • 5. The timing network that sets the output frequency of a 555 astable circuit contains ________.

    • Options
    • A. three external resistors are used
    • B. two external resistors and an external capacitor are used
    • C. an external resistor and two external capacitors are used
    • D. no external resistor or capacitor is required
    • Discuss
    • 6. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

    • Options
    • A. The logic level at the D input is transferred to Q on NGT of CLK.
    • B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
    • C. The Q output is ALWAYS identical to the D input when CLK = PGT.
    • D. The Q output is ALWAYS identical to the D input.
    • Discuss
    • 7. How many flip-flops are required to produce a divide-by-128 device?

    • Options
    • A. 1
    • B. 4
    • C. 6
    • D. 7
    • Discuss
    • 8. A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?

    • Options
    • A. The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.
    • B. The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.
    • C. A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.
    • D. A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.
    • Discuss
    • 9. For an S-R flip-flop to be set or reset, the respective input must be:

    • Options
    • A. installed with steering diodes
    • B. in parallel with a limiting resistor
    • C. LOW
    • D. HIGH
    • Discuss
    • 10. A 555 operating as a monostable multivibrator has an R1 of 220 kΩ. Determine C1 for a pulse width of 4 ms.

    • Options
    • A. 0.017 µF
    • B. 17 pF
    • C. 170 pF
    • D. 1,700 µF
    • Discuss


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