Discussion
Home ‣ Digital Electronics ‣ Flip-Flops Comments
- Question
Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below. Determine if the circuit is functioning properly, and if not, what might be wrong.
Options- A. The circuit is functioning properly.
- B. Q2 is incorrect; the flip-flop is probably bad.
- C. The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
- D. A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to reset.
- Correct Answer
- Q2 is incorrect; the flip-flop is probably bad.
- 1. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
Options- A. True
- B. False Discuss
- 2. Which of the following describes the operation of a positive edge-triggered D flip-flop?
Options- A. If both inputs are HIGH, the output will toggle.
- B. The output will follow the input on the leading edge of the clock.
- C. When both inputs are LOW, an invalid state exists.
- D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock. Discuss
- 3. What is one disadvantage of an S-R flip-flop?
Options- A. It has no enable input.
- B. It has an invalid state.
- C. It has no clock input.
- D. It has only a single output. Discuss
- 4. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
Options- A. parity error checking
- B. ones catching
- C. digital discrimination
- D. digital filtering Discuss
- 5. Which of the following best describes the action of pulse-triggered FF's?
Options- A. The clock and the S-R inputs must be pulse shaped.
- B. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
- C. A pulse on the clock transfers data from input to output.
- D. The synchronous inputs must be pulsed. Discuss
- 6. The symbols on this flip-flop device indicate ________.
Options- A. triggering takes place on the negative-going edge of the CLK pulse
- B. triggering takes place on the positive-going edge of the CLK pulse
- C. triggering can take place anytime during the HIGH level of the CLK waveform
- D. triggering can take place anytime during the LOW level of the CLK waveform Discuss
- 7. To completely load and then unload an 8-bit register requires how many clock pulses?
Options- A. 2
- B. 4
- C. 8
- D. 16 Discuss
- 8. A 555 operating as a monostable multivibrator has a C1 = 100 µF. Determine R1 for a pulse width of 500 ms.
Options- A. 45 Ω
- B. 455Ω
- C. 4.5 kΩ
- D. 455 kΩ Discuss
- 9. As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
Options- A. very long.
- B. very short.
- C. at a maximum value to enable the input control signals to stabilize.
- D. of no consequence as long as the levels are within the determinate range of value. Discuss
- 10. Propagation delay time, tPLH, is measured from the ________.
Options- A. triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
- B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
- C. preset input to the LOW-to-HIGH transition of the output
- D. clear input to the HIGH-to-LOW transition of the output Discuss
Flip-Flops problems
Search Results
Correct Answer: False
Correct Answer: The output will follow the input on the leading edge of the clock.
Correct Answer: It has an invalid state.
Correct Answer: ones catching
Correct Answer: The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
Correct Answer: triggering takes place on the negative-going edge of the CLK pulse
Correct Answer: 16
Correct Answer: 4.5 kΩ
Correct Answer: very short.
Correct Answer: triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
Comments
More in Digital Electronics:
Programming
Copyright ©CuriousTab. All rights reserved.
Eat a healthy diet each day