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  • Question
  • Which of the following best describes the action of pulse-triggered FF's?


  • Options
  • A. The clock and the S-R inputs must be pulse shaped.
  • B. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
  • C. A pulse on the clock transfers data from input to output.
  • D. The synchronous inputs must be pulsed.

  • Correct Answer
  • The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock. 


  • Flip-Flops problems


    Search Results


    • 1. With regard to a D latch, ________.

    • Options
    • A. the Q output follows the D input when EN is LOW
    • B. the Q output is opposite the D input when EN is LOW
    • C. the Q output follows the D input when EN is HIGH
    • D. the Q output is HIGH regardless of EN's input state
    • Discuss
    • 2. What is the difference between the 7476 and the 74LS76?

    • Options
    • A. the 7476 is master-slave, the 74LS76 is master-slave
    • B. the 7476 is edge-triggered, the 74LS76 is edge-triggered
    • C. the 7476 is edge-triggered, the 74LS76 is master-slave
    • D. the 7476 is master-slave, the 74LS76 is edge-triggered
    • Discuss
    • 3. Edge-triggered flip-flops must have:

    • Options
    • A. very fast response times.
    • B. at least two inputs to handle rising and falling edges.
    • C. a pulse transition detector.
    • D. active-LOW inputs and complemented outputs.
    • Discuss
    • 4. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.

    • Options
    • A. 1 kHz
    • B. 2 kHz
    • C. 4 kHz
    • D. 16 kHz
    • Discuss
    • 5. A 555 operating as a monostable multivibrator has a C1 = 0.01 µF. Determine R1 for a pulse width of 2 ms.

    • Options
    • A. 200 kΩ
    • B. 182 kΩ
    • C. 91 kΩ
    • D. 182 Ω
    • Discuss
    • 6. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.

    • Options
    • A. parity error checking
    • B. ones catching
    • C. digital discrimination
    • D. digital filtering
    • Discuss
    • 7. What is one disadvantage of an S-R flip-flop?

    • Options
    • A. It has no enable input.
    • B. It has an invalid state.
    • C. It has no clock input.
    • D. It has only a single output.
    • Discuss
    • 8. Which of the following describes the operation of a positive edge-triggered D flip-flop?

    • Options
    • A. If both inputs are HIGH, the output will toggle.
    • B. The output will follow the input on the leading edge of the clock.
    • C. When both inputs are LOW, an invalid state exists.
    • D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
    • Discuss
    • 9. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.

    • Options
    • A. True
    • B. False
    • Discuss
    • 10. Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below. Determine if the circuit is functioning properly, and if not, what might be wrong.


    • Options
    • A. The circuit is functioning properly.
    • B. Q2 is incorrect; the flip-flop is probably bad.
    • C. The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
    • D. A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to reset.
    • Discuss


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