Discussion
Home ‣ Digital Electronics ‣ Flip-Flops Comments
- Question
Edge-triggered flip-flops must have:
Options- A. very fast response times.
- B. at least two inputs to handle rising and falling edges.
- C. a pulse transition detector.
- D. active-LOW inputs and complemented outputs.
- Correct Answer
- a pulse transition detector.
- 1. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.
Options- A. 1 kHz
- B. 2 kHz
- C. 4 kHz
- D. 16 kHz Discuss
- 2. A 555 operating as a monostable multivibrator has a C1 = 0.01 µF. Determine R1 for a pulse width of 2 ms.
Options- A. 200 kΩ
- B. 182 kΩ
- C. 91 kΩ
- D. 182 Ω Discuss
- 3. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
Options- A. the clock pulse is LOW
- B. the clock pulse is HIGH
- C. the clock pulse transitions from LOW to HIGH
- D. the clock pulse transitions from HIGH to LOW Discuss
- 4. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
Options- A. active-HIGH
- B. active-LOW Discuss
- 5. In a 555 timer, three 5 kΩ resistors provide a trigger level of ________.
Options- A. 1/4 VCC and a threshold level 1/2 VCC
- B. 1/3 VCC and a threshold level 3/4 VCC
- C. 1/3 VCC and a threshold level 2/3 VCC
- D. 1/4 VCC and a threshold level 2/3 VCC Discuss
- 6. What is the difference between the 7476 and the 74LS76?
Options- A. the 7476 is master-slave, the 74LS76 is master-slave
- B. the 7476 is edge-triggered, the 74LS76 is edge-triggered
- C. the 7476 is edge-triggered, the 74LS76 is master-slave
- D. the 7476 is master-slave, the 74LS76 is edge-triggered Discuss
- 7. With regard to a D latch, ________.
Options- A. the Q output follows the D input when EN is LOW
- B. the Q output is opposite the D input when EN is LOW
- C. the Q output follows the D input when EN is HIGH
- D. the Q output is HIGH regardless of EN's input state Discuss
- 8. Which of the following best describes the action of pulse-triggered FF's?
Options- A. The clock and the S-R inputs must be pulse shaped.
- B. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
- C. A pulse on the clock transfers data from input to output.
- D. The synchronous inputs must be pulsed. Discuss
- 9. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
Options- A. parity error checking
- B. ones catching
- C. digital discrimination
- D. digital filtering Discuss
- 10. What is one disadvantage of an S-R flip-flop?
Options- A. It has no enable input.
- B. It has an invalid state.
- C. It has no clock input.
- D. It has only a single output. Discuss
Flip-Flops problems
Search Results
Correct Answer: 2 kHz
Correct Answer: 182 kΩ
Correct Answer: the clock pulse transitions from LOW to HIGH
Correct Answer: active-HIGH
Correct Answer: 1/3 VCC and a threshold level 2/3 VCC
Correct Answer: the 7476 is master-slave, the 74LS76 is edge-triggered
Correct Answer: the Q output follows the D input when EN is HIGH
Correct Answer: The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
Correct Answer: ones catching
Correct Answer: It has an invalid state.
Comments
There are no comments.More in Digital Electronics:
Programming
Copyright ©CuriousTab. All rights reserved.