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Home ‣ Digital Electronics ‣ Flip-Flops See What Others Are Saying!
  • Question

  • Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.


  • Options
  • A. 1 kHz
  • B. 2 kHz
  • C. 4 kHz
  • D. 16 kHz

  • Correct Answer
  • 2 kHz 

    • More questions

    • 1. An SPLD listed as 22V10 has ________.

    • Options
    • A. 10 inputs, 10 outputs, and requires a 22 V power source
    • B. 11 inputs, 11 outputs, and requires a 10 V power source
    • C. 22 inputs and 10 outputs
    • D. 10 inputs and 22 outputs
      • Discuss
    • 2. Which of the following combinations cannot be combined into K-map groups?

    • Options
    • A. corners in the same row
    • B. corners in the same column
    • C. diagonal
    • D. overlapping combinations
      • Discuss
    • 3. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.

    • Options
    • A. constantly LOW
    • B. constantly HIGH
    • C. a 20 kHz square wave
    • D. a 10 kHz square wave
      • Discuss
    • 4. The DSO ________, ________, and ________ analog waveforms.

    • Options
    • A. filters, conditions, sends
    • B. levels, stores, weighs
    • C. sends, receives, translates
    • D. digitizes, stores, displays
      • Discuss
    • 5. The difference between a PLA and a PAL is:

    • Options
    • A. The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane.
    • B. The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable AND plane.
    • C. The PAL has more possible product terms than the PLA.
    • D. PALs and PLAs are the same thing.
      • Discuss
    • 6. What should be done to unused inputs on TTL gates?

    • Options
    • A. They should be left disconnected so as not to produce a load on any of the other circuits and to minimize power loading on the voltage source.
    • B. All unused gates should be connected together and tied to V through a 1 k Ω resistor.
    • C. All unused inputs should be connected to an unused output; this will ensure compatible loading on both the unused inputs and unused outputs.
    • D. Unused AND and NAND inputs should be tied to VCC through a 1 kΩ resistor; unused OR and NOR inputs should be grounded.
      • Discuss
    • 7. The truth table shown below describes the operation of a NOR gate.


    • Options
    • A. True
    • B. False
      • Discuss
    • 8. The Boolean equation results from this Karnaugh map.


    • Options
    • A. True
    • B. False
      • Discuss
    • 9. The timing diagram for a two-input NAND gate is shown below. The gate is working correctly.


    • Options
    • A. True
    • B. False
      • Discuss
    • 10. The circuit given below has no output on Q1 when examined with an oscilloscope. All J-K inputs are HIGH, the CLK signal is present, and the Q0 is toggling. The C input of FF1 is a constant LOW. What could be causing the problem?


    • Options
    • A. The Q0 output should be connected to the J input of FF1.
    • B. The output of FF0 may be shorted to ground.
    • C. The input of FF1 may be shorted to ground.
    • D. Either the output of FF0 or the input of FF1 may be shorted to ground.
      • Discuss

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