logo

CuriousTab

CuriousTab

Discussion

Home ‣ Digital Electronics ‣ Flip-Flops Comments
  • Question

  • On a master-slave flip-flop, when is the master enabled?


  • Options
  • A. when the gate is LOW
  • B. when the gate is HIGH
  • C. both of the above
  • D. neither of the above

  • Correct Answer
  • when the gate is HIGH 

    • Flip-Flops problems

    Search Results

    • 1. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

    • Options
    • A. It can't be done.
    • B. Invert the Q outputs.
    • C. Invert the S-R inputs.
      • Discuss
    • 2. A J-K flip-flop is in a "no change" condition when ________.

    • Options
    • A. J = 1, K = 1
    • B. J = 1, K = 0
    • C. J = 0, K = 1
    • D. J = 0, K = 0
      • Discuss
    • 3. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

    • Options
    • A. cross coupling
    • B. gate impedance
    • C. low input voltages
    • D. asynchronous operation
      • Discuss
    • 4. The output pulse width for a 555 monostable circuit with R1 = 3.3 kΩ and C1 = 0.02 µF is ________.

    • Options
    • A. 7.3 µs
    • B. 73 µs
    • C. 7.3 ms
    • D. 73 ms
      • Discuss
    • 5. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

    • Options
    • A. 16
    • B. 8
    • C. 4
    • D. 2
      • Discuss
    • 6. Why are the S and R inputs of a gated flip-flop said to be synchronous?

    • Options
    • A. They must occur with the gate.
    • B. They occur independent of the gate.
      • Discuss
    • 7. The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are LOW. What could be causing the problem?


    • Options
    • A. There is no problem.
    • B. The clock should be held HIGH.
    • C. The PRE is stuck LOW.
    • D. The CLR is stuck HIGH.
      • Discuss
    • 8. An RC circuit used in a 74122 retriggerable one-shot has an REXT of 100 kΩ and a CEXT of 0.005 µF. The pulse width is ________.

    • Options
    • A. 70 µs
    • B. 16 µs
    • C. 160 µs
    • D. 32 µs
      • Discuss
    • 9. In VHDL, how is each instance of a component addressed?

    • Options
    • A. A name followed by a colon and the name of the library primitive
    • B. A name followed by a semicolon and the component type
    • C. A name followed by the library being used
    • D. A name followed by the component library number
      • Discuss
    • 10. What is the hold condition of a flip-flop?

    • Options
    • A. both S and R inputs activated
    • B. no active S or R input
    • C. only S is active
    • D. only R is active
      • Discuss

    Comments

    There are no comments.
Enter a new Comment




Aptitude

Engineering

Programming

Reasoning

Links

Copyright ©CuriousTab. All rights reserved.