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  • Question

  • A 555 timer is connected for astable operation as shown below along with the output waveform. It is determined that the duty cycle should be 0.5. What steps need to be taken to correct the duty cycle, while maintaining the same output frequency?

    A 555 timer is connected for astable operation as shown below along with the output waveform. It is


  • Options
  • A. Increase the value of C.
  • B. Increase Vcc and decrease RL.
  • C. Decrease R1 and R2.
  • D. Decrease R1 and increase R2.

  • Correct Answer
  • Decrease R1 and increase R2. 

    • Flip-Flops problems

    Search Results

    • 1. How many flip-flops are in the 7475 IC?

    • Options
    • A. 1
    • B. 2
    • C. 4
    • D. 8
      • Discuss
    • 2. The carry propagation can be expressed as ________.

    • Options
    • A. Cp = AB
    • B. Cp = A + B
    • C.
    • D.
      • Discuss
    • 3. The design concept of using building blocks of circuits in a PLD program is called a(n):

    • Options
    • A. hierarchical design.
    • B. architectural design.
    • C. digital design.
    • D. verilog.
      • Discuss
    • 4. When adding an even parity bit to the code 110010, the result is ________.

    • Options
    • A. 1110010
    • B. 1111001
    • C. 110010
    • D. 001101
      • Discuss
    • 5. What is the indication of a short to ground in the output of a driving gate?

    • Options
    • A. Only the output of the defective gate is affected.
    • B. There is a signal loss to all load gates.
    • C. The node may be stuck in either the HIGH or the LOW state.
    • D. The affected node will be stuck in the HIGH state.
      • Discuss
    • 6. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

    • Options
    • A. 16
    • B. 8
    • C. 4
    • D. 2
      • Discuss
    • 7. The output pulse width for a 555 monostable circuit with R1 = 3.3 kΩ and C1 = 0.02 µF is ________.

    • Options
    • A. 7.3 µs
    • B. 73 µs
    • C. 7.3 ms
    • D. 73 ms
      • Discuss
    • 8. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

    • Options
    • A. cross coupling
    • B. gate impedance
    • C. low input voltages
    • D. asynchronous operation
      • Discuss
    • 9. A J-K flip-flop is in a "no change" condition when ________.

    • Options
    • A. J = 1, K = 1
    • B. J = 1, K = 0
    • C. J = 0, K = 1
    • D. J = 0, K = 0
      • Discuss
    • 10. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

    • Options
    • A. It can't be done.
    • B. Invert the Q outputs.
    • C. Invert the S-R inputs.
      • Discuss

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