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  • Question

  • Which of the figures given below represents an OR gate?

    Which of the figures given below represents an OR gate? a b c d


  • Options
  • A. a
  • B. b
  • C. c
  • D. d

  • Correct Answer
  • a 

    • Describing Logic Circuits problems

    Search Results

    • 1. Which step in this reduction process is using DeMorgan's theorem?


    • Options
    • A. STEP 1
    • B. STEP 2
    • C. STEP 3
    • D. STEP 4
      • Discuss
    • 2. Identify the type of gate below from the equation

    • Options
    • A. Ex-NOR gate
    • B. OR gate
    • C. Ex-OR gate
    • D. NAND gate
      • Discuss
    • 3. Which type of gate can be used to add two bits?

    • Options
    • A. Ex-OR
    • B. Ex-NOR
    • C. Ex-NAND
    • D. NOR
      • Discuss
    • 4. The Ex-NOR is sometimes called the ________.

    • Options
    • A. parity gate
    • B. equality gate
    • C. inverted OR
    • D. parity gate or the equality gate
      • Discuss
    • 5. Select the statement that best describes the parity method of error detection:

    • Options
    • A. Parity checking is best suited for detecting double-bit errors that occur during the transmission of codes from one location to another.
    • B. Parity checking is not suitable for detecting single-bit errors in transmitted codes.
    • C. Parity checking is best suited for detecting single-bit errors in transmitted codes.
    • D. Parity checking is capable of detecting and correcting errors in transmitted codes.
      • Discuss
    • 6. A NOR gate with one HIGH input and one LOW input:

    • Options
    • A. will output a HIGH
    • B. functions as an AND
    • C. will not function
    • D. will output a LOW
      • Discuss
    • 7. What is the basic difference between AHDL and VHDL?

    • Options
    • A. ADHL is used in all PLD's.
    • B. VHDL is used in all PLD's.
    • C. ADHL is proprietary.
    • D. VHDL is proprietary.
      • Discuss
    • 8. The Boolean equation for a NOR function is:

    • Options
    • A.
    • B.
    • C.
    • D.
      • Discuss
    • 9. How are the statements between BEGIN and END not evaluated in VHDL?

    • Options
    • A. Constantly
    • B. Simultaneously
    • C. Concurrently
    • D. Sequentially
      • Discuss
    • 10. A NAND gate has:

    • Options
    • A. active-LOW inputs and an active-HIGH output.
    • B. active-LOW inputs and an active-LOW output.
    • C. active-HIGH inputs and an active-HIGH output.
    • D. active-HIGH inputs and an active-LOW output.
      • Discuss

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