Discussion
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- Question
Decoupling capacitors should be tied from VCC on one device to ground on a different device.
Options- A. True
- B. False
- Correct Answer
- False
- 1. Is the propagation delay from the clock to the output for the 7476 the same as the delay from the set or reset to the output?
Options- A. yes
- B. no Discuss
- 2. Which of the following circuit parameters would be most likely to limit the maximum operating frequency of a flip-flop?
Options- A. setup and hold time
- B. clock pulse HIGH and LOW time
- C. propagation delay time
- D. clock transition time Discuss
- 3. What is the difference between setup time and hold time?
Options- A. Setup time occurs after the active clock edge, hold time occurs before the active clock edge.
- B. Setup time occurs before the active clock edge, hold time occurs after the active clock edge.
- C. Setup time and hold time both occur at the active clock edge. Discuss
- 4. A settable flip-flop's normal starting state when power is first applied to a circuit is always the ________ state.
Options- A. reset
- B. set
- C. toggle
- D. dual Discuss
- 5. In the automatic reset circuit for a flip-flop, how long does it take the capacitor to completely charge?
Options- A. 1 time constant (RC)
- B. 2 time constants (RC)
- C. 5 time constants (RC)
- D. 10 time constants (RC) Discuss
- 6. The purpose of a pull-up resistor is to keep a terminal at a ________ level when it would normally be at a ________ level.
Options- A. LOW, float
- B. HIGH, float
- C. clock, float
- D. pulsed, float Discuss
- 7. Why does the data sheet for the 7476 only give a minimum value for the clock pulse width (both HIGH and LOW)?
Options- A. nominal value
- B. best-case condition
- C. worst-case condition Discuss
- 8. A Schmitt trigger:
Options- A. has two trip points
- B. is a zero crossing detector
- C. has positive feedback
- D. has two trip points and positive feedback Discuss
- 9. A Schmitt trigger has VT+ = 2.0 V and VT? = 1.2 V. What is the hysteresis voltage of the Schmitt trigger?
Options- A. 0.4 volt
- B. 0.6 volt
- C. 0.8 volt
- D. 1.2 volts Discuss
- 10. Why should a LED be pulled LOW from a logic gate rather than pulled HIGH?
Options- A. LOW-level current is smaller.
- B. LOW-level current is larger.
- C. HIGH-level current is larger.
- D. LOW-level current is smaller and HIGH-level current is larger. Discuss
Digital Design problems
Search Results
Correct Answer: yes
Correct Answer: propagation delay time
Correct Answer: Setup time occurs before the active clock edge, hold time occurs after the active clock edge.
Correct Answer: set
Correct Answer: 5 time constants (RC)
Correct Answer: HIGH, float
Correct Answer: worst-case condition
Correct Answer: has two trip points and positive feedback
Correct Answer: 0.8 volt
Correct Answer: LOW-level current is larger.
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