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Question
What is the difference between setup time and hold time?
Options
A. Setup time occurs after the active clock edge, hold time occurs before the active clock edge.
B. Setup time occurs before the active clock edge, hold time occurs after the active clock edge.
C. Setup time and hold time both occur at the active clock edge.
Correct Answer
Setup time occurs before the active clock edge, hold time occurs after the active clock edge.
More questions
1. A slice consists of ________.
Options
A. only two logic cells
B. between 2 and 8 logic cells
C. up to 16 logic cells
D. a single CLB
Show Answer
Scratch Pad
Discuss
Correct Answer: only two logic cells
2. In the digital clock project, frequency prescaling is used to take a 1 pps input and transform it into a 60 pps timing signal.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: False
3. To transmit parallel data over a serial cable, the data must first go through data conversion to the serial format.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: True
4. A gated S-R flip-flop goes into the SET condition when
S
is HIGH,
R
is LOW, and
EN
is HIGH.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: True
5. A CPLD is basically a simplified PLD.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: False
6. The largest truth table that can be implemented directly with an 8-line-to-1-line MUX has ________.
Options
A. 3 rows
B. 4 rows
C. 8 rows
D. 16 rows
Show Answer
Scratch Pad
Discuss
Correct Answer: 8 rows
7. Which one of the following is an embedded function of the Stratix II FPGA?
Options
A. AND-OR logic
B. Programmable SOP
C. Digital signal processing
D. None of the above
Show Answer
Scratch Pad
Discuss
Correct Answer: Digital signal processing
8. The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________.
Options
A. multiplexing, 1
B. parallel-to-serial conversion, 0
C. demultiplexing, 0
D. parallel-to-serial conversion, HIGH
Show Answer
Scratch Pad
Discuss
Correct Answer: parallel-to-serial conversion, 0
9. In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.
Options
A. function
B. signal
C. semicolon
D. colon
Show Answer
Scratch Pad
Discuss
Correct Answer: colon
10. In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.
Options
A. traffic
B. D
C. flip-flop
D. clock
Show Answer
Scratch Pad
Discuss
Correct Answer: clock
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