What would be the output voltage of a 7814 voltage regulator? ?14 V dc +14 V dc

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Correct Answer

+14 V dc

1. The circuit in Figure 9-8 is defective; data is not appearing on the output lines. A check with the scope shows data pulses on the serial data line and multiplex control lines, S0?S2; no parity error is indicated. A further check with a logic probe indicates that V_cc and ground appear to be present. What might be wrong with the circuit?
Options
A. The demultiplexer may be bad.
B. The parity checker is defective.
C. The parity generator may be bad.
D. The parity checker is defective, or the parity generator may be bad.

2. For the input values (A0?A3, B0?B3, Data Select = 1) given for the circuit given below, what will be indicated on the displays?
Options
A. A = 0, B = 5
B. A = 5, B = 0
C. A = 6, B = 0
D. A = 0, B = 6

3. Refer to the display multiplexer given below. The MSD display is blank, while the LSD seems to be OK. The input and output lines to the 74157 and 7449 are checked with a scope and can be seen changing levels. The A input on the 74139 also changes; however, the 0 output on the 74139 is always LOW and the 1 output is always HIGH. The B and EN inputs on the 74139 are always LOW. What could cause the problem and what should be done to correct it?
Options
A. The 74139 is defective; replace it.
B. The EN pin on the 74139 could have a bad connection; check the connection.
C. The 74139 is defective and must be replaced; or the EN pin on the 74139 could have a bad connection, which should be checked.
D. The MSD display is bad; replace it.

4. In an AHDL BCD to binary code converter, how is multiplication by 10 accomplished?
Options
A. By using the shifting of bits
B. By using the library multiplication function
C. By using integer types
D. By using the multiplication operator

7. Setup time specifies:
Options
A. the minimum time the control levels need to be maintained on the inputs prior to the triggering edge of the clock in order to be reliably clocked into the flip-flop
B. the maximum time interval required for the control levels to remain on the inputs before the triggered edge of the clock in order for the data to be reliably clocked out of the flip-flop
C. how long the operator has to get the flip-flop running before the maximum power level is exceeded
D. how long it takes the output to change states after the clock has transitioned

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